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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 63/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
Hardware Slave Mode
After reset, the ADuC845/ADuC847/ADuC848 default to
hardware slave mode. The I
2
C interface is enabled by clearing
the SPE bit in SPICON. Slave mode is enabled by clearing the
I2CM bit in I2CCON. The parts have a full hardware slave. In
slave mode, the I
2
C address is stored in the I2CADD register.
Data received or to be transmitted is stored in the I2CDAT
register.
Rev. A | Page 63 of 108
Once enabled in I
2
C slave mode, the slave controller waits for
a start condition. If the parts detect a valid start condition,
followed by a valid address, followed by the R/W bit, then the
I2CI interrupt bit is automatically set by hardware. The I
2
C
peripheral generates a core interrupt only if the user has pre-
configured the I
2
C interrupt enable bit in the IEIP2 SFR as well
as the global interrupt bit, EA, in the IE SFR. Therefore,
MOV IEIP2, #01h
SETB EA
;Enable I
2
C Interrupt
An autoclear of the I2CI bit is implemented on the parts so that
this bit is cleared automatically upon read or write access to the
I2CDAT SFR.
MOV I2CDAT, A
MOV A, I2CDAT
;I2CI auto-cleared
;I2CI auto-cleared
If for any reason the user tries to clear the interrupt more than
once, that is, access the data SFR more than once per interrupt,
the I
2
C controller stops. The interface then must be reset by
using the I2CRS bit.
The user can choose to poll the I2CI bit or to enable the
interrupt. In the case of the interrupt, the PC counter vectors to
003BH at the end of each complete byte. For the first byte, when
the user gets to the I2CI ISR, the 7-bit address and the R/W bit
appear in the I2CDAT SFR.
The I2CTX bit contains the R/W bit sent from the master. If
I2CTX is set, the master is ready to receive a byte; therefore the
slave transmits data by writing to the I2CDAT register. If I2CTX
is cleared, the master is ready to transmit a byte; therefore the
slave receives a serial byte. Software can interrogate the state of
I2CTX to determine whether it should write to or read from
I2CDAT.
Once the part has received a valid address, hardware holds
SCLOCK low until the I2CI bit is cleared by software. This
allows the master to wait for the slave to be ready before
transmitting the clocks for the next byte.
The I2CI interrupt bit is set every time a complete data byte is
received or transmitted, provided that it is followed by a valid
ACK. If the byte is followed by a NACK, an interrupt is not
generated.
The part continues to issue interrupts for each complete data
byte transferred until a stop condition is received or the interface
is reset.
When a stop condition is received, the interface resets to a state
in which it is waiting to be addressed (idle). Similarly, if the
interface receives a NACK at the end of a sequence, it also
returns to the default idle state. The I2CRS bit can be used to
reset the I
2
C interface. This bit can be used to force the interface
back to the default idle state.
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| ADUC847BCP8-3 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC845BCP8-5 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC847BCP8-5 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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相關代理商/技術參數 |
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| ADUC845_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter?? Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC845BCP32-3 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
| ADUC845BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
| ADUC845BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP |
| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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