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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 65/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
SPICON—SPI Control Register
Rev. A | Page 65 of 108
SFR Address:
Power-On Default:
Bit Addressable:
F8H
05H
Yes
Table 41. SPICON SFR Bit Designations
Bit No.
Name
7
ISPI
Description
SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user code to enable SPI functionality.
Cleared by user code to enable standard Port 2 functionality.
SPI Master/Slave Mode Select Bit.
Set by user code to enable master mode operation (SCLOCK is an output).
Cleared by user code to enable slave mode operation (SCLOCK is an input).
Clock Polarity Bit.
Set by user code to enable SCLOCK idle high.
Cleared by user code to enable SCLOCK idle low.
Clock Phase Select Bit.
Set by user code if the leading SCLOCK edge is to transmit data.
Cleared by user code if the trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Bits.
SPR1
SPR0
Selected Bit Rate
0
0
f
core
/2
0
1
f
core
/4
1
0
f
core
/8
1
1
f
core
/16
6
WCOL
5
SPE
4
SPIM
3
CPOL
1
2
CPHA
1
1, 0
SPR1, SPR0
1
The CPOL and CPHA bits should both contain the same values for master and slave devices.
Note that both SPI and I
2
C use the same ISR (Vector Address 3BH); therefore, when using SPI and I
2
C simultaneously, it is necessary to
check the interfaces following an interrupt to determine which one caused the interrupt.
SPIDAT: SPI Data Register
SFR Address:
7FH
Power-On Default: 00H
Bit Addressable:
No
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