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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 64/108頁 |
| 文件大?。?/td> | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
SPI SERIAL INTERFACE
Rev. A | Page 64 of 108
The ADuC845/ADuC847/ADuC848 integrate a complete
hardware serial peripheral interface (SPI) interface on-chip. SPI
is an industry-standard synchronous serial interface that allows
8 bits of data to be synchronously transmitted and received
simultaneously, that is, full duplex. Note that the SPI pins are
multiplexed with the Port 2 pins (P2.0, P2.1, P2.2, and P2.3).
These pins have SPI functionality only if SPE is set. Otherwise,
with SPE cleared, standard Port 2 functionality is maintained.
SPI can be configured for master or slave operation and typically
consists of pins SCLOCK, MISO, MOSI, and SS.
SCLOCK (Serial Clock I/O Pin)
Pin 28 (MQFP Package), Pin 30 (CSP Package)
The master clock (SCLOCK) is used to synchronize the data
transmitted and received through the MOSI and MISO data
lines.
A single data bit is transmitted and received in each SCLOCK
period. Therefore, a byte is transmitted/received after eight
SCLOCK periods. The SCLOCK pin is configured as an output
in master mode and as an input in slave mode. In master mode,
the bit rate, polarity, and phase of the clock are controlled by the
CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see
Table 41). In slave mode, the SPICON register must be configured
with the same phase and polarity (CPHA and CPOL) as the
master. The data is transmitted on one edge of the SCLOCK
signal and sampled on the other.
MISO (Master In, Slave Out Pin)
Pin 30 (MQFP Package), Pin 32 (CSP Package)
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte-wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In Pin)
Pin 29 (MQFP Package), Pin31 (CSP Package)
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte-wide (8-bit)
serial data, MSB first.
SS (Slave Select Input Pin)
Pin 31 (MQFP Package), Pin 33 (CSP Package)
The SS pin is used only when the ADuC845/ADuC847/
ADuC848 are configured in SPI slave mode. This line is active
low. Data is received or transmitted in slave mode only when
the SS pin is low, allowing the parts to be used in single-master,
multislave SPI configurations. If CPHA = 1, the SS input can be
pulled low permanently. If CPHA = 0, the SS input must be
driven low before the first bit in a byte-wide transmission or
reception and must return high again after the last bit in that
byte-wide transmission or reception. In SPI slave mode, the
logic level on the external SS pin (Pin 31/ Pin 33) can be read
via the SPR0 bit in the SPICON SFR.
The SFR register in Table 41 is used to control the SPI interface.
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相關代理商/技術參數 |
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| ADUC845BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
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| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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