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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 80/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
UART SERIAL INTERFACE
The serial port is full duplex, meaning that it can transmit and
receive simultaneously. It is also receive buffered, meaning that
it can begin receiving a second byte before a previously received
byte is read from the receive register. However, if the first byte is
still not read by the time reception of the second byte is complete,
the first byte is lost. The physical interface to the serial data
network is via Pins RxD(P3.0) and TxD(P3.1), while the SFR
interface to the UART comprises SBUF and SCON, as described
below.
Rev. A | Page 80 of 108
Table 54. SCON SFR Bit Designations
Bit No.
Name
7, 6
SM0, SM1
SBUF SFR
Both the serial port receive and transmit registers are accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register, and reading SBUF accesses a
physically separate receive register.
SCON UART—Serial Port Control Register
SFR Address:
Power-On Default:
Bit Addressable:
98H
00H
Yes
Description
UART Serial Mode Select Bits. These bits select the serial port operating mode as follows:
SM0
SM1
Selected Operating Mode.
0
0
Mode 0: Shift register, fixed baud rate (Core_Clk/2).
0
1
Mode 1: 8-bit UART, variable baud rate.
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16).
1
1
Mode 3: 9-bit UART, variable baud rate.
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as
the byte of data is received.
In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. Cleared by user software to disable
serial port reception.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
SBUF—UART Serial Port Data Register
SFR Address:
Power-On Default:
Bit Addressable:
99H
00H
No
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