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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 61/108頁 |
| 文件大?。?/td> | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
I
2
C SERIAL INTERFACE
The ADuC845/ADuC847/ADuC848 support a fully licensed
I
2
C serial interface. The I
2
C interface is implemented as a full
hardware slave and software master. SDATA (Pin 27 on the
MQFP package and Pin 29 on the CSP package) is the data I/O
pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the CSP
package) is the serial interface clock for the SPI interface. The
I
2
C interface on the parts is fully independent of all other pin/
function multiplexing. The I
2
C interface incorporated on the
ADuC845/ADuC847/ADuC848 also includes a second address
register (I2CADD1) at SFR Address F2H with a default power-
on value of 7FH. The I
2
C interface is always available to the user
and is not multiplexed with any other I/O functionality on the
chip. This means that the I
2
C and SPI interfaces can be used at
the same time.
Table 40. I2CCON SFR Bit Designations
Bit No.
Name
Description
7
MDO
I
2
C Software Master Data Output Bit (master mode only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable bit (MDE) is set.
6
MDE
I
2
C Software Output Enable Bit (master mode only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx).
5
MCO
I
2
C Software Master Clock Output Bit (master mode only).
This bit is used to implement the SCLK for a master I
2
C transmitter in software. Data written to this bit is output on
the SCLK pin.
4
MDI
I
2
C Software Master Data Input Bit (master mode only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA pin is latched into
this bit on an SCLK transition if the data output enable (MDE) bit is 0.
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
2
I2CRS
I
2
C Reset Bit (slave mode only).
Set by the user to reset the I
2
C interface.
Cleared by the user code for normal I
2
C operation.
1
I2CTX
I
2
C Direction Transfer Bit (slave mode only).
Set by the MicroConverter if the I
2
C interface is transmitting.
Cleared by the MicroConverter if the I
2
C interface is receiving.
0
I2CI
I
2
C Interrupt Bit (slave mode only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared by the MicroConverter when the user code reads the I2CDAT SFR. I2CI should not be cleared by user code.
Rev. A | Page 61 of 108
Note that when using the I
2
C and SPI interfaces simultaneously,
they both use the same interrupt routine (Vector Address 3BH).
When an interrupt occurs from one of these, it is necessary to
interrogate each interface to see which one has triggered the ISR
request.
The four SFRs are used to control the I
2
C interface are
described next.
I2CCON—I
2
C Control Register
SFR Address:
Power-On Default:
Bit Addressable:
E8H
00H
Yes
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