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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 77/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters
0 and 1. Unless otherwise noted, these modes of operation are
the same for both Timer 0 and Timer 1.
Rev. A | Page 77 of 108
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 52 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
0
CORE
CLK*
CONTROL
P3.4/T0
GATE
P3.2/INT0
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
C/T = 0
C/T = 1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 52. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an interrupt.
The counted input is enabled to the timer when TR0 = 1 and
either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to
be controlled by external input INT0 to facilitate pulse-width
measurements. TR0 is a control bit in the special function
register TCON; Gate is in TMOD. The 13-bit register consists of
all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of
TL0 are indeterminate and should be ignored. Setting the run
flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 53.
CORE
CLK*
CONTROL
P3.4/T0
GATE
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
0
P3.2/INT
C/T = 0
C/T = 1
Figure 53. Timer/Counter 0, Mode 1
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload as shown in Figure 54. Overflow from
TL0 not only sets TF0, but also reloads TL0 with the contents of
TH0, which is preset by software. The reload leaves TH0
unchanged.
CONTROL
TF0
(8TL0
INTERRUPT
RELOAD
TH0
(8 BITS)
CORE
CLK*
P3.4/T0
GATE
TR0
0
0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
P3.2/INT
C/T = 0
C/T = 1
Figure 54. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 55. TL0
uses the Timer 0 control bits C/T, Gate, TR0, INT0, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. Therefore,
TH0 then controls the Timer 1 interrupt. Mode 3 is provided
for applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can still be
used by the serial interface as a baud rate generator. In fact, it
can be used in any application not requiring an interrupt from
Timer 1 itself.
CONTROL
CORE
CLK/12
TF0
(8TL0
INTERRUPT
CORE
CLK*
P3.4/T0
GATE
TR0
TF1
TH0
(8 BITS)
INTERRUPT
CORE
TR1
0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
0
P3.2/INT
C/T = 0
C/T = 1
Figure 55. Timer/Counter 0, Mode 3
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