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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 10/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
21 22 23
24 25 26
27 28
A[7:0]
I
Register Select Address Input.
These inputs provide the
address for the specific internal register to be accessed for a
selected port. These inputs are clocked in on falling edges of
WR and RD.
Note:
Pin #21 = A7, Pin # 28 = A0
18
BUSSIZE
I
Register Interface Bus Size Select.
1 = Register Interface Bus is 16 Bits Wide (CDST[15:0])
0 = Register Interface Bus is 8 Bits Wide (CDST[7:0])
14
13
BE1
BE0
I
Register Byte Enable Inputs.
These inputs determine which
bytes of the current 16-bit word on CDST[15:0] contain valid
data. The inputs are clocked in on falling edges of WR and RD.
11 = No Valid Data
10 = Valid data on CDST[7:0]
01 = Valid data on CDST[15:8]
00 = Valid data on CDST[15:0]
35 36 37
38 39 42
43 44 45
46 47 50
51 52 53
54
CDST[15:0]
I/O
Register Data Input.
This bidirectional bus is the 16-bit data
path to and from the internal registers for a selected port. Data
is read from/written to the internal registers on falling edges of
WR and RD. These pins are high impedance until their output
drivers are enabled by RD and ENREGIO being asserted low.
Note:
Pin #35 = CDST 15, Pin #54 = CDST 0
57
READY
O
Register Ready Indication Output.
This active high output
indicates that data being read out on CDST[15:0] is valid.
READY goes active high after RD has been asserted, and stays
high until RD is deasserted. READY goes into High Impedance
State when ENREGIO is deasserted.
34
33
32
31
INT_1
INT_2
INT_3
INT_4
O
Interrupt Output.
These outputs, one per port, are asserted
active high when certain interrupt bits are asserted. These pins
remain latched high until all interrupt bits causing the interrupt
condition are read.
Miscellaneous
174
197
220
243
FDUPLX_1
FDUPLX_2
FDUPLX_3
FDUPLX_4
I
Full Duplex Mode Input.
1 = Half Duplex
0 = Full Duplex
Full Duplex mode can also be selected by setting the Full
Duplex bit in the Configuration 2 register. Half-Duplex mode is
selected when both this pin and the Full Duplex mode bit are
set to Half Duplex.
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
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