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參數資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數: 37/128頁
文件大小: 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
37 of 128
April, 2002
interrupt disable bit in the Configuration 1 register.
Table 14
describes all
the bits that assert interrupt and their associated enable/disable bits.
3.5.10 MAC Control Frame Check
The length/type field is checked to detect whether the packet is a valid
MAC Control frame. Refer to
Section 3.16, “MAC Control Frames,”
page 52
, for more details on MAC Control frames.
3.6 Transmit FIFO
3.6.1 General
The transmit FIFO acts as a temporary buffer between the System
Interface and transmit MAC section. The transmit FIFO size is 128 bytes.
Data is clocked into the transmit FIFO with the System Interface clock,
SCLK. Data is automatically clocked out of the transmit FIFO with the
PHY Interface TXC clock whenever (1) a full packet is loaded into the
FIFO (evidenced by an EOF being written into the FIFO on the System
Interface), or (2) the FIFO data exceeds the Transmit Control threshold
setting. There is one programmable watermark output and one almost
empty output which aid in managing the data flow into the transmit FIFO.
3.6.2 Transmit Control Threshold
The Transmit Control feature causes a packet in the transmit FIFO to be
automatically transmitted once the transmit FIFO data exceeds the
Transmit Control threshold or a full packet has been loaded into the
transmit FIFO (an EOF write occurred for that packet).
The Transmit Control threshold is programmable over the entire 128 byte
transmit FIFO range. The Transmit Control threshold can be programmed
with the four Transmit Control threshold setting bits that reside in the
Transmit Control/Product ID register. Once the data in the FIFO exceeds
this threshold, then the packet is automatically transmitted to the MAC
and over the PHY Interface.
3.6.3 Watermark
There is one watermark for the transmit FIFO. This watermark is output
on the TXRDY pin. This watermark is asserted when the transmit FIFO
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相關代理商/技術參數
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