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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 43/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
43 of 128
April, 2002
3.9.4 Discard Output Indication
When a packet that is being receive/transmitted over the System
Interface has been automatically discarded, the TXRET and RXDC
output pins are asserted to indicate that the discard happened. TXRET
and RXDC are normally latched high when a discard takes place. TXRET
and RXDC for the selected port can be cleared low by asserting the
clearing pin, CLRTXERR, and CLRRXERR, respectively.
When TXRET and RXDC are asserted, all data is prevented from being
written to the transmit and receive FIFOs, respectively, as long as the
respective signals are latched high. When these signals are cleared, then
the respective FIFOs can be written to.
3.10 Receive Status Word
3.10.1 General
A 32-bit status word can be appended to the end of each receive data
packet and stored in the receive FIFO. This status word contains a byte
count and error information for the receive data packet.
3.10.2 Format and Bit Order
The format for the status word is shown in
Table 8
. The top 16-bits
contain the actual byte count for the packet, and the bottom 16-bits
contain the status information related to the packet.
Table 7
Receive Discard Conditions
Discard Condition
Description
Receive FIFO Overflow
Receive FIFO full.
CRC Error
Receive packet has CRC error.
Oversize Packet
Receive packet is greater than maximum packet size, exclusive of pream-
ble and SFD. Maximum packet size is programmable between 1518-1533
bytes.
Undersize Packet
Receive packet is less than 64 bytes, exclusive of preamble and SFD.
RXABORT Pin
RXABORT pin was asserted while receive packet was read out on System
Interface.
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