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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 30/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
packet has been loaded in the transmit FIFO. This function is described
in more detail in
Section 3.6, “Transmit FIFO,” page 37
.
3.4.7 AutoRetransmission Upon Collision
In Half Duplex mode, the device will automatically retransmit a packet
that has been interrupted due to a collision. This is described in more
detail in
Section 3.8, “Collision,” page 40
.
3.4.8 TX Status
Each port contains two TX Status registers that store the status of the
last two packets transmitted. With each transmission attempt, successful
or not, one of the status registers is written with the status for that packet.
When a TX Status register is written, the transmit status update bit is set
in that register to indicate that the register contains new information. The
data remains latched in the TX Status registers until it is read out via the
Register Interface. When a TX Status register is read, the transmit status
update bit is cleared low to indicate that it does not contain new data
since the last read. After a TX Status Resister has been read, that
register is available to be written with new status information for another
packet.
These two TX Status registers share the same register address. If both
registers contain new status information, the first read to that register
address will give the status of the second to last packet transmitted, and
the second read will give the status of the last packet transmitted.
There are three register bits that can modify the operation of the TX
Transmit Status registers:
1.
The TX Status registers can be disabled, i.e. status is never loaded
into them, by setting the transmit status disable bit in the
Configuration 2 register.
2.
The TX Status registers can be configured to update continuously
and not stay latched until read by setting the transmit status register
update select bit in the Configuration 2 register.
3.
The TX Status registers can be configured to not store status for
packets affected by a collision by setting the transmit status disable
bit in the Configuration 3 register.
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