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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 6/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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6 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
192
215
238
5
RXOVF_1
RXOVF_2
RXOVF_3
RXOVF_4
O
Receive FIFO Overflow Output.
1 = RX FIFO Full
0 = Not Full
These outputs, one per port, are clocked out on rising edges of
the system clock, SCLK.
127
RXTXEOF
I/O
Receive-Transmit End of Frame Input/Output.
This bidirec-
tional pin indicates that the current data word, for the selected
port, is the last double word of the packet. During receive FIFO
reads, this pin is an output and is asserted active high when the
last word of a receive packet is being read out of the receive
FIFO on RXTXDATA[31:0]. During transmit writes, this pin is an
input and needs to be asserted active high when the last word
of the packet is being written into the transmit FIFO on RXTX-
DATA[31:0]. This signal is clocked in/out on rising edges of the
system clock, SCLK.
128
TXNOCRC
I
Transmit No CRC Input.
1 = CRC is not Appended
0 = CRC is Calculated and Appended to Current Transmit
Packet being Input on System Interface
This input is clocked in on rising edges of the system clock,
SCLK, and is for the selected port.
75 76 77
78 81 82
83 84 87
88 89 90
93 94 95
96 102
103 104
105 108
109 110
111 114
115 116
117 120
121 122
123
RXTXDATA[31:0]
I/O
Receive-Transmit Data Input/Output.
This bidirectional bus
contains data read or written to/from the FIFOs for the selected
port. During receive reads, these pins are outputs and contain
data read from the receive FIFO. During transmit reads, these
pins are inputs and contain data to be written to the transmit
FIFO. RXTXDATA[31:0] is clocked in/out on rising edges of the
system clock, SCLK.
Note:
Pin #75 = RXTXDATA 31, Pin #123 = RXTXDATA 0
131
139
147
155
RXABORT_1
RXABORT_2
RXABORT_3
RXABORT_4
I
Receive Abort Input.
1 = Abort Packet, Discard RX FIFO Data, Block RX FIFO Input
Until Start of Next Packet.
0 = No Discard
These inputs, one per port, are clocked in on rising edges of the
system clock, SCLK.
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
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