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參數資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數: 48/128頁
文件大小: 997K
代理商: L84302
48 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
3.12.2 Data Format and Bit Order
Figure 6
shows the format of an MI data transfer cycle (defined in IEEE
802.3 Clause 22).
Table 9
defines each bit transmitted over the MI.
Figure 6
MI Frame Format and Bit Order
IDLE31 is shifted out first on MDIO
Table 9
MI Bit Definitions
Symbol
Name
I/O
Definition
Source of Bits
IDLE[31:0]
Idle Pattern
O
These 32 bits are always 1’s, and they pro-
vide the necessary spacing between MI
data transfer cycles.
Internally generated
ST1
ST0
Start Bits
O
These two bits contain the 01 pattern. This
pattern (following an Idle Pattern) signals
the start of an MI data transfer cycle.
Internally generated
OP1
OP0
Opcode
Select
O
10 = Read cycle
01 = Write cycle
MI Command/Status
1 Register
PHYAD[4:0]
Physical
Device
Address
O
These bits contain the address of the exter-
nal PHY that is selected for the MI data
transfer.
MI Command/Status
1 Register
REGAD4
[4:0]
Register
Address
O
These bits contain the address of the regis-
ter in the external PHY that is selected for
the MI data transfer.
MI Command/Status
0 Register
TA1
TA0
Turn-
around
Time
I/O
These bits provide turnaround time for
MDIO between write and read operations.
For Write Cycle Output TA[1:0] = 10
For Read Cycle, Input TA[1:0] = Z0
Internally generated
D[15:0]
Data
I/O
These bits contain data to/from the selected
register in the selected external PHY.
MI Data 0-1 Registers
MDC
MDIO
(Write)
MDIO
(Read)
1
0
31
.....
0
1
2
3
4
9
14
15
16
31
5
8
.....
10
13
....
17
30
....
1
1
1
0
1
0
1
P4
P3
P0
R4
R3
R0
1
0
D15 D14
D1
D0
1
1
1
0
1
1
0
P4
P3
P0
R4
R3
R0
0
D15
D14
D1
D1
D0
D[15:0]
TA[1:0]
REGAD[4:0]
PHYAD[4:0]
OP[1:0]
ST[1:0]
IDLE[31:0]
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