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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 23/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
23 of 128
April, 2002
or after TXINTEN is asserted, TXWREN has to be asserted to actually
start the write operation. If TXWREN is then asserted while TXINTEN is
asserted, the data word on the RXTXDATA[31:0] I/O pins is clocked into
the transmit FIFO on each rising edge of the SCLK clock for the port
selected by the RXTXPS[1:0] inputs. TXINTEN and TXWREN can be
continuously asserted and deasserted as many times as desired while a
packet is being written into the device. The last word of the packet must
be indicated to the device by asserting RXTXEOF on the same SCLK
rising edge that clocks in the last word of the packet. TXWREN does not
need to be deasserted between the end of one packet and the start of
the next. RXTXDATA[31:0] input data is 32-bit wide packet data whose
format and relationship to the MAC packet and PHY Interface is
described in
Figure 4
.
The byte enable pins, RXTXBE[3:0], are used for both transmit and
receive operation, and they determine which bytes of the 32-bit
RXTXDATA[31:0] data word contain valid data. RXTXBE[3:0] are inputs
during a transmit write operation, and are clocked in on rising edges of
SCLK along with each RXTXDATA[31:0] data word. The correspondence
between the byte enable inputs and the valid bytes of each data word on
RXTXDATA[31:0] is defined in
Table 2
. Any logic combination of
RXTXBE[3:0] inputs is allowed, with the one exception that RXTXBE[3:0]
must not be 1111.
The end of frame I/O pin, RXTXEOF, indicates which data word is the
last word of the Ethernet data packet. RXTXEOF is configured to be an
input during a write operation. RXTXEOF is input on the same SCLK
rising edge as the first and last word of the data packet.
There are four transmit FIFO ready outputs, one per port, on the
TXRDY_[1:4] pins. The transmit FIFO ready output is a transmit FIFO
Table 2
Byte Enable Pin vs. Valid Byte Position
RXTXBE[3:0] Pins
Valid Byte Position on RXTXDATA[31:0]
RXTXBE3
RXTXDATA[31:24]
RXTXBE2
RXTXDATA[23:16]
RXTXBE1
RXTXDATA[15:8]
RXTXBE0
RXTXDATA[7:0]
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