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參數(shù)資料
型號(hào)： L84302
元件分類： 通用總線功能
英文描述： L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述： L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日
文件頁數(shù)： 88/128頁
文件大?。?/td> 997K
代理商： L84302
88 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
Bit 0 occurs on CDST0/CDST8 pin
Table 34
RX Status Register Definition
7
6
5
4
3
2
1
0
RXUPDATE
R/LH
12BYTES
R/LHI
GOOD_RX
R/LHI
OSIZE
R/LHI
USIZE
R/LHI
DRIBBLE
R/LH
CRC
R/LHI
OVF
R/LH
Bit
Symbol
Name
Definition
R/W
Def.
7
RXUPDATE
Receive Status
Updated
1 = Status has not been updated since
last read
0 = Updated
R/LH
1
6
12BYTES
First 12 Bytes
Detect
1 = First 12 bytes of the packet have been
received
0 = Not received
R/LHI
0
5
GOOD_RX
Good Receive
Packet Detect
1 = Receive packet was good, i.e. had no
errors
0 = No good
R/LHI
0
4
OSIZE
Oversize Packet
Detect
1 = Receive packet was oversize
0 = No error
R/LHI
0
3
USIZE
Undersize
Packet Detect
1 = Receive packet was undersize
0 = No error
R/LHI
0
2
DRIBBLE
Dribble Error
Detect
1 = Receive packet had dribble bits or
nibbles
0 = No error
R/LH
0
1
CRC
CRC Error
Detect
1 = Receive packet had CRC error
0 = No error
R/LHI
0
0
OVF
RX FIFO Over-
flow Detect
1 = Receive packet corrupted by RX FIFO
overflow
0 = No error
R/LHI
0
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