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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁數(shù)： | 46/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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46 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
(COL). The transmit and receive clocks operate at 25 MHz in 100 Mbps
mode and 2.5 MHz in 10 Mbps mode.
3.11.4 MII Transmit Operation
On the transmit side, TXC must be continuously input at a frequency of
25 MHz in 100 Mbps mode and 2.5 MHz in 10 Mbps mode. When no
data is to be transmitted, TXEN is deasserted, TXER is held low, and
TXD[3:0] are held low. When packet data is to be transmitted, TXEN is
asserted on the rising edge of TXC, and data on TXD[3:0] is clocked out
on rising edges of the TXC clock output while TXEN is asserted active
high. TXD[3:0] input data is nibble wide packet data whose format needs
to be the same as specified in IEEE 802.3 and shown in
Figure 4
. To
terminate the transmission of a packet, TXEN is deasserted on the same
rising edge of TXC as the last data nibble.
3.11.5 MII Receive Operation
On the receive side, RXC must be continuously input at a frequency of
25 MHz in 100 Mbps mode and 2.5 MHz in 10 Mbps mode. When data
not being sent from an external Physical Layer device, CRS has to be
input low, RXDV has to be input low, RXER has to be input low, and any
data on RXD[3:0] is ignored. An external Physical Layer device signals
the start of a packet to the device by asserting CRS and holding it
asserted for the entire packet reception. While CRS is asserted, valid
data is indicated to the device when RXDV is asserted on the falling edge
of RXC. While RXDV is asserted, data on RXD[3:0] is considered valid
and input to the receive MAC on falling edges of RXC. The RXD[3:0] data
has the same frame structure as the TXD[3:0] data and is specified in
IEEE 802.3 and shown in
Figure 4
. The end of packet is detected when
CRS and RXDV are deasserted.
RXER is a receive error input which is asserted by the external Physical
Layer device when it detects an error on a data nibble. RXER is asserted
on the falling edge of RXC for the duration of the RXC clock cycle during
which the nibble containing the error is being input on RXD[3:0]. Per
IEEE 802.3 specifications, packets with containing RXERs are treated as
if the FCS value is incorrect.
The collision input, COL, is asserted by the Physical Layer device
whenever it detects the collision condition.
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