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參數資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數： | 55/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
55 of 128
April, 2002
3.16.3 Transmitter Pause Disable
Receive MAC Control frames normally pause the transmitter. Receive
MAC Control frames can be programmed to not pause the transmitter by
clearing the MAC Control frame enable bit in the Configuration 4
Register. When this bit cleared low, received Pause frames do not affect
the transmitter.
3.16.4 Passthrough to FIFO
Receive MAC Control frames are normally discarded and not passed to
the receive FIFO. Receive MAC Control frames can be passed to the
receive FIFO by appropriately setting the MAC Control frame
passthrough bits in the Configuration 4 register. These bits allow either
all MAC Control frames or just non-Pause frames to be passed to the
receive FIFO.
3.16.5 Reserved Multicast Address Disable
Receive MAC Control frames are normally rejected as invalid if they do
not have the reserved multicast address in the destination address field.
Receive MAC Control frames can be accepted without regard to the
contents of the destination address field by appropriately setting the MAC
Control frame address filter bit in the Configuration 4 register. When this
bit is cleared low, any value in the destination address field will be
accepted as a valid address.
3.17 Reset
The device has three resets, which are described in
Table 11
.
From
Table 11
, note that the device reset is controlled by a pin, and it
must be asserted at powerup in order to properly initialize the device.
When this device reset is initiated, it forces the other two reset bits to
their default states of logic 1; these two reset bits must then be cleared
to logic 0 for normal device operation to begin.
The RESET pin or bit should be asserted for a minimum of 10
μ
s. During
the RESET period, the TXC and RXC input clocks from the external PHY
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