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參數資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數： 103/172頁
文件大小： 1035K
代理商： MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
103
QILR determines the priority level of interrupts requested by the QSM.
ILQSPI[2:0] — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI[2:0] — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the ex-
ception table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should
be written to QIVR during QSM initialization.
After initialization, QIVR determines which two vectors in the exception vector table are to be used
for QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to
each other. Both submodules use the same interrupt vector with the least significant bit (LSB) de-
termined by the submodule causing the interrupt.
The value of INTV0 used during an interrupt-acknowledge cycle is supplied by the QSM. During an
interrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated for
an SCI interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect.
Reads of INTV0 return a value of one.
7.3.2 Pin Control Registers
The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/
O on a pin-by-pin basis.
Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
driving incorrect data, the first byte to be output must be written before DDRQS is configured.
DDRQS must then be written to determine the direction of data flow and to output the value con-
tained in register PORTQS. Subsequent data for output is written to PORTQS.
QILR
— QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
ILQSPI[2:0]
ILSCI[2:0]
QIVR
RESET:
0
0
0
0
0
0
0
0
QIVR
— QSM Interrupt Vector Register
$YFFC05
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QILR
INTV[7:0]
RESET:
0
0
0
0
1
1
1
1
相關PDF資料
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MC68HC9D60 Advance Information - Rev 4.0
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相關代理商/技術參數
參數描述
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MC68HC98LJ12CFUE 功能描述:8位微控制器 -MCU 8 BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC9S08RC60 L33R DIE 制造商:Motorola Inc 功能描述:
MC68HCP11A1CFN3 功能描述:8位微控制器 -MCU 8-bit HCMOS single chip MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HCP11A1FN 制造商:MOTORALA 功能描述:
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