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參數資料
型號: MC68HC916X1
廠商: Motorola, Inc.
英文描述: 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述: 16位微控制器模塊(16位模塊化微控制器)
文件頁數: 33/172頁
文件大小: 1035K
代理商: MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
33
3.7.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. Ex-
ternal RESET assertion can be delayed internally for a period equal to the longest bus cycle time
(or the bus monitor time-out period) to protect write cycles from being aborted by reset. While
RESET is asserted, SCIM pins are either in an inactive, high-impedance state or are driven to their
inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal
into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT
cycles after it detects that the RESET signal is no longer being externally driven, to guarantee this
length of reset to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of
512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues
to assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10
cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level
one, reset exception processing begins. If, however, the reset input is at logic level zero, the reset
control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes
to high-impedance state for ten cycles, then it is tested again. The process repeats until RESET is
released.
Table 20 Module Pin Functions
Module
ADC
Pin Mnemonic
PADA[7:0]/AN[7:0]
VRH
VRL
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
PCLK
PWMA, PWMB
PQS7/MOSI
PQS6/MISO
PQS5/SCK
PQS4/PCS3
PQS3/PCS2
PQS2/PCS1
PQS1/PCS0/SS
PQS0/TXD
RXD
Function
Discrete Input
Reference Voltage
Reference Voltage
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Output
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
RXD
CPU
GPT
QSM
相關PDF資料
PDF描述
MC68HC9D60 Advance Information - Rev 4.0
MC68HC12D60 Advance Information - Rev 4.0
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