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參數資料
| 型號： | MC68HC916X1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁數： | 128/172頁 |
| 文件大小： | 1035K |
| 代理商： | MC68HC916X1 |
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MOTOROLA
128
MC68HC916X1
MC68HC916X1TS/D
LAT — Latch Control
0 = Programming latches disabled
1 = Programming latches enabled
The LAT bit configures the EEPROM array for normal reads or for programming. When LAT is cleared,
the FLASH module address and data buses are connected to the IMB address and data buses and the
module is configured for normal reads. When LAT is set, module address and data buses are connected
to parallel internal latches and the array is configured for programming or erasing.
Once LAT is set, the next write to a valid FLASH module address causes the programming circuitry to
latch both address and data. Unless control register shadow bits are to be programmed, the write must
be to an array address. The value of LAT cannot be changed while ENPE = 1.
ENPE — Enable Programming/Erase
0 = Disable program/erase voltage
1 = Apply program/erase voltage to flash EEPROM
Setting the ENPE bit applies the program/erase voltage to the array. ENPE can be set only after LAT
has been set and a write to the data and address latches has occurred. ENPE remains cleared if these
conditions are not met. While ENPE is set, the LAT, VFPE, and ERAS bits cannot be changed, and at-
tempts to read an array location are ignored.
FEE1BS[3:0]
— Flash EEPROM Bootstrap Words
FEE2BS[3:0]
— Flash EEPROM Bootstrap Words
The flash EEPROM bootstrap words (FEE1BS[3:0], FEE2BS[3:0]) can be used as system boot-
strap vectors. When BOOT = 1 in FEExMCR during reset, the flash module responds to program
space accesses of IMB addresses $000000 to $000006 after reset. When BOOT = 0, the flash mod-
ule responds only to normal array and register accesses. FEExBS[3:0] can be read at any time, but
it can only be changed by programming the appropriate locations.
Table 68
shows bootstrap word
addresses in program space.
$YFF810–$YFF816
$YFF830–$YFF836
9.6 Flash EEPROM Operation
The following paragraphs describe the operation of the flash EEPROM module during reset, system
boot, normal operation, and while it is being programmed or erased.
9.6.1 Reset Operation
Reset initializes all registers to certain default values. Some of these reset values are programma-
ble by the user and are contained in flash EEPROM shadow registers. If the state of the STOP
shadow bit is zero, and bus pin DATA14 is pulled high during reset, the STOP bit in the FEExMCR
is cleared during reset. The array responds normally to the bootstrap address range and the flash
EEPROM array base address. If the STOP shadow bit is one, or the module’s associated data bus
pin is pulled low during reset, the STOP bit in the FEExMCR is set. The flash EEPROM array is
disabled until the STOP bit is cleared by software. It will not respond to the bootstrap address range,
or the flash EEPROM array base address in FEExBAH and FEExBAL, allowing an external device
to respond to the flash EEPROM array's address space or bootstrap information. Since the erased
state of the shadow bits is one, erased flash EEPROM modules (which include the shadow registers
in the control blocks) come out of reset in STOP mode.
Table 68 Bootstrap Words
Bootstrap Word
Corresponding
Boot Address
$000000
$000002
$000004
$000006
Corresponding
Vector Content
Initial ZK, SK, and PC
Initial PC
Initial SP
Initial IZ
FEE1BS0, FEE2BS0
FEE1BS1, FEE2BS1
FEE1BS2, FEE2BS2
FEE1BS3, FEE2BS3
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