
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
139
1.
2.
Turn on V
FPE2K
(apply program/erase voltage to V
FPE2K
pin).
Clear ERAS and set LAT and VFPE bits in BFECTL to set program mode, enable program-
ming address and data latches, and invoke special verification read circuitry. Set initial val-
ue of t
ppulse
to t
pmin
.
Write new data to the desired address. This causes the address and data of the location to
be programmed to be latched in the programming latches.
Set ENPE to apply programming voltage.
Delay long enough for one programming pulse to occur (t
ppulse
).
Clear ENPE to remove programming voltage.
Delay while high voltage is turning off (t
vprog
).
Read the location just programmed. If the value read is all zeros, proceed to step 9. If not,
calculate a new value for t
ppulse
and repeat steps 4 through 7 until either the location is ver-
ified or the total programming time (t
progmax
) has been exceeded. If t
progmax
has been ex-
ceeded, the location may be bad and should not be used.
If the location is programmed, calculate t
pmargin
and repeat steps 4 through 7. If the location
does not remain programmed, the location is bad.
10. Clear VFPE and LAT.
11. If there are more locations to program, repeat steps 2 through 10.
12. Turn off V
FPE2K
(reduce voltage on V
FPE2K
pin to V
DD
).
13. Read the entire array to verify that all locations are correct. If any locations are incorrect,
the array is bad.
3.
4.
5.
6.
7.
8.
9.
10.5.4.2 Erasure Sequence
Use the following procedure to erase the BEFLASH. Refer to
Figures
45
and
46
in
11 Electrical
Characteristics
for V
FPE
to V
DD
relationships during erasure.
1.
2.
3.
4.
Turn on V
FPE2K
(apply program/erase voltage to V
FPE2K
pin).
Set initial value of t
epulse
to t
emin
.
Set LAT, VFPE, and ERAS bits to configure the BEFLASH module for erasure.
Write to any valid address in the control block or array. This allows the erase voltage to be
turned on. The data written and the address written to are of no consequence.
Set ENPE to apply programming voltage.
Delay long enough for one erase pulse to occur (t
epulse
).
Clear ENPE to remove programming voltage.
Delay while high voltage is turning off (t
verase
).
Clear LAT, ERAS, and VFPE to allow normal access to the BEFLASH.
10. Read the entire array and control block to ensure that the entire module is erased.
11. If all of the locations are not erased, calculate a new value for t
epulse
and repeat steps 3
through 10 until either the remaining locations are erased or the maximum erase time
(t
erasemax
) has expired.
12. If all locations are erased, calculate t
emargin
and repeat steps 3 through 10. If all locations
do not remain erased, the BEFLASH module may be bad.
13. Turn off V
FPE2K
(reduce voltage on V
FPE2K
pin to V
DD
).
5.
6.
7.
8.
9.