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參數資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統基礎芯片
文件頁數: 15/81頁
文件大小: 323K
代理商: UJA1061
2004 Mar 22
15
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.4.2
W
ATCHDOG WINDOW BEHAVIOUR
Whenever the UJA1061 has entered Normal mode as a
result of a successful watchdog initialization, the Window
mode of the watchdog has been activated. This makes
sure that the microcontroller operates within the desired
speed. Too fast as well as too slow operation will be
detected. See Fig.5 for watchdog triggering using the
Window mode.
The UJA1061 provides ten different period timings in this
mode (with an accuracy of
±
10 %).
The watchdog window has been defined to be between
50 and 100 % of the nominal programmed watchdog
period.
The period can be changed on the fly with any valid SPI
mode register access. Whenever the watchdog is
triggered within the window time, the timer is reset in order
to start a new period.
Any too early or too late watchdog access or wrong mode
registercodeaccessresultsinanimmediatesystemreset,
entering Start-up mode.
In the background, any enabled interrupt event will be
monitored by the watchdog. If the microcontroller does not
react upon receipt of an interrupt within the interrupt
response time (265 ms), a system reset will be performed.
handbook, full pagewidth
MCE626
trigger window
trigger
window
too early
trigger
restarts
period
50 %
trigger
via SPI
trigger
via SPI
last
trigger point
earliest possible
trigger point
latest possible
trigger point
earliest
possible
trigger
point
latest
possible
trigger
point
too early
trigger restarts period
(with different duration if
desired)
period
100 %
50 %
100 %
new period
Fig.5 Watchdog triggering using Window mode.
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