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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片 |
| 文件頁數(shù)： | 56/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
56
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.16
Test modes
6.16.1
S
OFTWARE DEVELOPMENT MODE
The Software Development mode is intended to support
software developers, writing and pre-testing the
application software without working around the watchdog
triggering and without unwanted jumps to Fail-safe mode.
This allows easy software development and debugging
without forcing unintended reset events. Instead of resets
caused by watchdog overflows, window missing, interrupt
time-out or exceeded start-up time an interrupt will be
forced instead of a reset. Once this mode is set, any
watchdog trigger failure will not result in a reset, only in an
interrupt, if enabled. Nevertheless the reset source
information and interrupt information continues to be
provided to the software as if there was a real reset event.
Furthermore, the interrupt monitoring, forcing a LOW
signal at pin RSTN if not serving the interrupt in time, is
disabled too. Also the watchdog initialization time
monitoring and reset monitoring have been disabled.Thus
the software can already trigger the watchdog as intended
for the final software version and any watchdog interrupt
gives an indication about pending watchdog trigger
problems. Once there are no further unwanted interrupts,
the watchdog can be used as intended.
In addition to the disabling of the watchdog activity, the
interrupt monitoring and the reset monitoring, any
transition to Fail-safe mode is disabled; the UJA1061 then
stays in the mode in which the problem occurred.
Transitions to Restart mode are still possible, but not to
Fail-safe mode. A V1 undervoltage of more than 256 ms is
the only exception that results in entering Fail-safe mode
and this is in order is to protect the UJA1061.
The Software Development mode can be used also for
testing and/or measuring many parameters/mode
changes during the pretest and final test programs.
For fail-safe reasons, the Software Development mode
can be activated by setting the ISDM bit via the Special
Mode register. This mode can be set only once after a first
battery connection before the watchdog is initialized, this
means within the 256 ms start-up period and before the
first SPI write-access to any other register. A second
possibility to enter this mode is a HIGH level (7 to 8 V) at
pin TEST before the battery is applied to BAT42. Leaving
this development mode and entering the normal operating
behaviour is executed after disabling the SDM bit at any
time during a write-access to the mode register. It should
be noted that the SDM bit has to confirm the Software
Development mode with each Mode Register access,
even if the TEST pin is pulled to a voltage higher than (7 to
8) V. Entering the Software Development mode again is
possible only by disconnection of the battery supply
(BAT42) thus forcing a new power-on period for the
UJA1061.
The watchdog behaviour within Standby and Sleep mode
is not affected by the SDM bit. This allows the cyclic
wake-up behaviour to be evaluated during the Standby or
Sleep mode of the UJA1061.
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相關(guān)代理商/技術(shù)參數(shù) |
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| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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