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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 71/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
71
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
LIN-transceiver (pins LIN, TXDL and RXDL)
; note 1
δ
1
duty factor 1
(2)
V
th(rec)(max)
= 0.744
×
V
SUP
;
V
th(dom)(max)
= 0.581
×
V
SUP
;
LSC = logic 0; t
bit
= 50
μ
s;
L42C = logic 0 with
V
SUP
= V
BAT14
= 7 to 18 V
or
L42C = logic 1 with V
BAT42
≥
18 V;
V
SUP
= internal 12 V
V
th(rec)(min)
= 0.284
×
V
SUP
;
V
th(dom)(min)
= 0.422
×
V
SUP
;
LSC = logic 0; t
bit
= 50
μ
s;
L42C = logic 0 with
V
SUP
= V
BAT14
= 7.6 to 18 V
or
L42C = logic 1 with V
BAT42
≥
18 V;
V
SUP
= internal 12 V
V
th(rec)(max)
= 0.778
×
V
SUP
;
V
th(dom)(max)
= 0.616
×
V
SUP
;
LSC = logic 1; t
bit
= 96
μ
s;
L42C = logic 0 with
V
SUP
= V
BAT14
= 7 to 18 V
or
L42C = logic 1 with V
BAT42
≥
18 V;
V
SUP
= internal 12 V
V
th(rec)(min)
= 0.251
×
V
SUP
;
V
th(dom)(min)
= 0.389
×
V
SUP
;
LSC = logic 1; t
bit
= 96
μ
s;
L42C = logic 0 with
V
SUP
= V
BAT14
= 7.6 to 18 V
or
L42C = logic 1 with V
BAT42
≥
18 V;
V
SUP
= internal 12 V
C
RXD
= 20 pF
0.396
δ
2
duty factor 2
(3)
0.581
δ
3
duty factor 3
(2)
0.417
δ
4
duty factor 4
(3)
0.590
t
p(rx1)r
, t
p(rx1)f
,
t
p(rx2)r
, t
p(rx2)f
t
p(rx1)(sym)
propagation delay of
receiving nodes 1 and 2
symmetry of propagation
delay of receiver
dominant time for
wake-up the
LIN-transceiver
continuously dominant
clamped LIN-bus
detection time
continuously dominant
clamped LIN-bus
recovery time
TXDL permanent
dominant disable time
time-out period between
wake-up message and
confirm message
6
μ
s
rising edge with respect to falling
edge; C
RXD
= 20 pF
Off-line
2
+2
μ
s
t
BUS(LIN)
30
150
μ
s
t
LIN(dom)(det)
Active mode; LIN = logic 0 V
40
160
ms
t
LIN(dom)(rec)
Active mode
tbf
1
tbf
ms
t
TXDL(dom)(dis)
Active mode; TXDL = 0 V
20
80
ms
t
timeout
Selective Sleep mode
115
285
ms
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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相關代理商/技術參數 |
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|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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