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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 45/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
45
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.9
S
YSTEM
C
ONFIGURATION
F
EEDBACK REGISTER
This register allows the settings within the Configuration register to be read back.
Table 10
SCF - System Configuration Feedback register (address 10) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
10
0
1
read System Configuration Feedback register (SCF)
read the System Configuration Feedback register without
writing to the System Configuration register
read the System Configuration Feedback register and write
to the System Configuration register (previous content
reflected)
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
1.5 V; exceeding this level may force an interrupt
0.75 V; exceeding this level may force an interrupt
20 ms system reset is selected; default after power-up
1 ms system reset is selected
Cyclic mode 2; 350
μ
s ON/32 ms period
Cyclic mode 1; 350
μ
s ON/16 ms period
continuously ON
OFF
the reduced V1 undervoltage threshold is selected
the normal V1 undervoltage threshold is selected
an increasing V1 current causes a reset event if the
watchdog was disabled
an increasing V1 current just activates the watchdog again
wake-up functionality at WAKE pin enabled
wake-up functionality at WAKE pin disabled
WAKE mode cyclic sample
WAKE mode continuous sample
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
INH pin HIGH
INH pin floating
0
11
reserved
0
10
reserved
0
9
GSTHC
GND Shift Threshold
Control
1
0
1
0
11
10
01
00
1
0
1
8
RLC
Reset Length Control
7, 6
V3C
V3 Control
5
V1RTHC
V1 Reset Threshold
Control
4
V1CMC
V1 Current Monitor
Control
0
1
0
1
0
0
3
WEN
WAKE Enable
2
WSC
WAKE Sample
Control
1
reserved
0
IC
INH control
1
0
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相關代理商/技術參數 |
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|---|---|
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