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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 21/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
21
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
The RAM status monitor monitors the V1 voltage. If
V1 voltage is lower than the minimum voltage needed for
the microcontroller RAM while V1 is active, then the
corresponding SPI bit will be set. This bit can be read by
the microcontroller when V1 has recovered (no reset is
generated).
Dependingontheversion-dependentoutputvoltageof V1,
theundervoltageresetthresholdaswellastheRAMstatus
monitor threshold are adapted accordingly.
The V1 regulator is protected against overload. The
maximum output current allowed at pin V1 depends on the
inputvoltageconnectedtopin BAT14.Theclosertheinput
voltage comes to the V1 output voltage, the more output
current can be sourced by the regulator. This feature is
very useful in combination with an external DC/DC
converter in providing a BAT14 voltage close to V1 (7 V,
for example).
6.6.3.2
V2 voltage regulator
The second independent voltage regulator V2 provides a
5 V supply for the CAN transmitter. The pin V2 is intended
for the connection of external buffering capacitors.
V2 is controlled autonomously by the CAN physical layer
and is activated upon any detected CAN-bus activity, or is
activated if the CAN physical layer is enabled by the
application microcontroller. This supply is short-circuit
protected and will be disabled in case of an overload
situation. The status of V2 will be reflected to the
application via dedicated interrupt and status flags.
6.6.4
S
WITCHED BATTERY OUTPUT
(V3)
V3 is a high-side switched BAT42-related output to drive
external loads such as wake-up switches or relays. The
features of V3 are as follows:
Supports three application controlled modes of
operation; On, Off or Cyclic mode
Two different Cyclic modes allow the supply of external
wake-up switches; these switches are powered
intermittently (for 384
μ
s every 16 ms or for 384
μ
s
every 32 ms) thus reducing the systems’ power
consumption in case a switch is continuously active; the
wake-up input of the UJA1061 is synchronized with the
V3 cycle time.
The switch is protected against short-circuits to ground
and current overloads. In case regulator V3 is
overloaded, pin V3 is automatically disabled, the
corresponding mode bit is reset and an interrupt is
forced, if enabled. If the UJA1061 was in Sleep mode
(V1 off), a wake-up is forced and the corresponding
reset source code becomes available within the reset
source register; this signals to the application that the
wake-up source via V3-supplied wake-up switches has
been lost.
6.7
CAN transceiver
The integrated fault-tolerant CAN transceiver of the
UJA1061isanadvancedISO11898-3compliantversionof
the TJA1054/TJA1054A and is fully inter-operable with
these two stand-alone transceivers.
The improvements and extensions of the integrated
fault-tolerant CAN transceiver-cell compared with the
TJA1054/TJA1054A are the following:
Enhancederrorsignalling;allbusfailuresareseparately
forwarded to the SPI register
Handling and reporting of clamping situations on CAN
and RXD/TXD interface
Ground shift detection with two selectable warning
levels to detect possible local GND problems before the
CAN communication is affected
Supports Selective Sleep mode with global wake-up
message filter
Improved wake-up filtering for CANL
No recovery of bus failures during mode changes
between Normal mode or low power modes
42 V system support for CANL low power termination.
6.7.1
M
ODE CONTROL
Different to existing stand-alone fault-tolerant CAN
transceivers,theintegratedautonomouscontrollerdefines
the mode of the CAN transceiver. This implies that the
fault-tolerant CAN transceiver, which is supplied by its
dedicated V2 supply, supports the bus failure
management and bus levels in all modes and
independently from the microcontroller. This ensures that
even a failing microcontroller (or failing V1 supply) does
not influence the communication of the rest of the CAN
network. Furthermore fail-safe behaviour is guaranteed in
all modes to protect the system against unwanted power
consumption.
The controller of the CAN physical layer provides two
major modes of operation of the CAN transceiver, the
Active mode and the Auto mode (see Fig.9).
Two dedicated CAN status bits (CANMD) are available to
indicate to the application whether the transceiver is in
Normal, On-line, Selective Sleep or Off-line mode.
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相關代理商/技術參數 |
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| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
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