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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎芯片 |
| 文件頁數： | 30/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
30
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
The following SPI interface signals are implemented:
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power
concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH.
The SPI interface can be accessed only when pin RSTN
(input channel of RSTN) is set HIGH.
Possible SPI failures are:
SPI clock count failure (wrong number of clock cycles
during one SPI access). Within one SCS cycle only
16 clock periods are allowed. Any deviation from the
16 clock cycles results in an SPI failure interrupt, if
enabled. The access is ignored by the UJA1061. In
Start-up and Restart mode, a reset is forced instead of
an interrupt
Wrong mode register code. The following events result
in an immediate system reset without interrupt
according to the state diagram of the system controller
– Mode other than initializing Normal mode selected
within mode register in Start-up or Restart mode
– Initializing Flash mode outside of Start-up mode or
within Start-up mode without previous Flash
sequence
– Bit WDD set in the mode register; this bit may only be
set via the special mode register
– Illegal watchdog period coding, see Section 6.14.2.
Illegal mode register code during Normal or Standby
mode of the UJA1061.
With a read-only access to the system status register or
the system diagnosis register which, with the mode
register, share the same SPI address, the data written to
the mode register is ‘don’t care’ and is ignored. Reading
these two system registers is allowed at any time
independent of watchdog window cycles.
handbook, full pagewidth
SCK
01
sampled
floating
floating
MCE634
X
X
MSB
14
13
12
01
LSB
MSB
14
13
12
01
LSB
X
SDI
SDO
02
03
04
15
16
Fig.13 SPI timing protocol.
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