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參數(shù)資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 68/81頁
文件大小: 323K
代理商: UJA1061
2004 Mar 22
68
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Note
1.
Not tested during production.
LIN-bus termination resistor connection (pin RTLIN)
V
O
output voltage
I
RTLIN
=
10
μ
A; L42C = logic 1;
V
BAT42
18 V
Normal mode; V
LIN
= 12 V (rec)
Normal mode; V
LIN
= 0 V;
t > t
LIN(dom)
Off-line mode; V
LIN
= 12 V (rec)
Normal mode; I
RTLIN
=
10
μ
A
to
10 mA; L42C = logic 0
(V
LIN
= V
BAT14(rec)
)
or
L42C = logic 1
(V
LIN(rec)
= 12 V; V
BAT42
18 V)
Normal mode; V
RTLIN
= 0 V;
V
LIN
= 0 V (t > t
LIN(dom)
)
Off-line mode; V
RTLIN
= 0 V;
L42C = logic 0 (V
LIN
= V
BAT14(rec)
)
or
L42C = logic 1 (V
LIN(rec)
= 12 V;
V
BAT42
18 V)
Off-line mode; V
RTLIN
= 0 V;
V
LIN
= 0 V (t > t
LIN;dom
)
V
10.8
9
11.4
12
12.0
15
V
V
9
12
250
15
500
V
mV
V
RTLIN
RTLIN load
regulation
I
O(pu)
RTLIN pull-up
current
150
75
35
μ
A
150
75
35
μ
A
I
O(RTLIN)
low-level leakage
current
10
0
+10
μ
A
TEST input (pin TEST)
V
th(TEST)
threshold voltage
threshold voltage
pull-down resistor
for entering Watchdog-OFF mode
for entering forced Normal mode
between pin TEST and GND
3
8
2
5
10
4
7
12
8
V
V
k
R
(pd)TEST
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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