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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 35/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
35
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.3
S
YSTEM STATUS REGISTER
This register allows status information to be read-back from the UJA1061.
Table 4
STAT- System Status register (address 00) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
00
0
1
read System Status register (STAT)
read System Status register without writing to Mode
register
read System Status register and write to Mode register
Power-on reset; first connection of BAT42 or BAT42 below
power-on voltage threshold
or
RSTN was forced LOW
externally
cyclic wake-up out of Sleep mode
low V1 supply; V1 has dropped below the reset threshold
V1 current above threshold within Standby mode of the
UJA1061 while watchdog OFF behaviour was selected and
the RESET option is selected within the System
Configuration register
V3 voltage is down due to short-circuit occurring during
Sleep mode
reserved
UJA1061 ready to enter Flash Programming mode
wake-up event via CAN while reset behaviour selected
or
during Sleep mode
wake-up event via LIN while reset behaviour selected
or
during Sleep mode
wake-up event via WAKE while reset behaviour selected
or
during Sleep mode
wake-up event out of Fail-safe mode
watchdog overflow (Normal operating mode)/time-out
(Standby mode/Flash mode); trigger too late
watchdog not initialized in time; 256 ms exceeded
watchdog triggered too early; window missed
illegal Mode Register Code
interrupt not served in time (within 256 ms)
reserved for future use; in order to stay compatible with
future silicon versions using this bit, software should ignore
this bit value
pin WAKE is above the threshold
pin WAKE is below the threshold
reserved for future use; in order to stay compatible with
future silicon versions using this bit, software should ignore
this bit value
0
11 to 8
RSS[3:0]
Reset Source
(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
7
reserved
6
LWS
Level Wake Status
1
0
0
5
reserved
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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