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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 6/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
6
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
5
PINNING
SYMBOL
PIN
DESCRIPTION
n.c.
n.c.
TXDL
1
2
3
not connected
not connected
transmit data input to activate the LIN output drive; LOW = LIN-bus dominant;
HIGH = LIN-bus recessive
regulated supply voltage output for microcontroller; voltage is 5 V, 3.3 V, 3 V
or 2.5 V according to version
receive data output for reading data from the LIN-bus; LOW when LIN-bus is
dominant; HIGH when LIN-bus is recessive
active LOW push-pull output used to reset the microcontroller; the UJA1061 also
monitors the voltage on pin RSTN for any clamping situation (fail-safe)
active LOW open-drain output used to interrupt the microcontroller; pin INTN is to
be wire-ANDed with other interrupt outputs within the ECU
push-pull enable output related to voltage regulator V1; active HIGH if the watchdog
is triggered successfully and a control bit is set; immediately pulled LOW with any
reset event (e.g. a watchdog overflow); full set/clear application access via SPI
while watchdog is served properly
SPI data input
SPI data output
SPI clock input
active LOW select input used to enable an SPI access
transmit data input that activates the CAN output driver; LOW = CAN-bus dominant;
HIGH = CAN-bus recessive
receive data output for reading data from the CAN-bus; LOW when CAN-bus is
dominant; HIGH when CAN-bus is recessive; output is continuously LOW upon a
wake-up event received via the CAN-bus
not connected
test pin; connect to ground in application
14 V battery related inhibit output for system extension, or ‘limp home’ output,
activated in Fail-safe mode (default floating)
42 V battery related local wake-up input
CAN termination resistor connection; in case of a CANL bus wire error this line is
terminated with a selectable impedance
regulated 5 V supply output reserved for CAN transceiver; an external buffer
capacitor connects to this pin
CAN-bus line; HIGH in dominant state and LOW in recessive state
CAN-bus line; LOW in dominant state and HIGH in recessive state
ground
CAN termination resistor connection; in case of a CANH bus wire error this line is
terminated with a selectable impedance
LIN-bus line; LOW when LIN-bus is dominant, HIGH when LIN-bus is recessive
LIN-bus termination resistor connection
14 V battery supply input
not connected
V1
4
RXDL
5
RSTN
6
INTN
7
EN
8
SDI
SDO
SCK
SCS
TXDC
9
10
11
12
13
RXDC
14
n.c.
TEST
INH/LIMP
15
16
17
WAKE
RTL
18
19
V2
20
CANH
CANL
GND
RTH
21
22
23
24
LIN
RTLIN
BAT14
n.c.
25
26
27
28
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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