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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 29/81頁 |
| 文件大小： | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
29
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
V
WAKE
sample
active
V
3
flip flop
V
INTM
mce633
t
w(CS)
= 384
μ
s
t
on(CS)
= 16 or 32 ms
t
su(CS)
= 256
μ
s
approx. 70 %
button pushed
button released
signal remains LOW
due to biasing (history)
signal already HIGH
due to biasing (history)
Fig.12 Pin WAKE, cyclic sampling via V3.
6.11
Interrupt output
In order to support multiple interrupt sources within a
system, pin INTN provides an open-drain output
configuration.
Whenever at least one bit is set within the interrupt register
this pin is forced LOW. Reading the interrupt register
clears all set bits. Only these bits are cleared as they have
definitely been read during that access.
The interrupt register will be cleared also during a system
reset (RSTN LOW).
6.12
Temperature protection
The temperature of the UJA1061 chip is monitored as long
as the microcontroller voltage regulator V1 is active.
To avoid any unexpected shut-down of the application by
the UJA1061, the temperature protection will not switch off
any part of the UJA1061 or activate a defined system stop
of its own accord. A too-high temperature only generates
an interrupt to the microcontroller, if enabled, and the
corresponding status bit is set. The microcontroller can
now decide whether to switch off parts of the UJA1061 in
order to decrease the chip temperature.
6.13
SPI interface
The Serial Peripheral Interface (SPI) provides the
communication link with the microcontroller and supports
multi-slave and multi-master operation. The SPI is
configured for full duplex data transfer; while new control
data is shifted-in, status information is automatically
returned. All registers provide a read-only access option.
Thus all status bits can be read back by the application at
any time.
The SPI interface with a data rate up to 2 Mbit/s provides
four interface signals, including chip select (see Fig.13).
Any bit-sampling is performed with the falling clock edge
and the data is shifted with the rising clock edge.
All SPI interface signals are derived from V1 in order to
avoid problems with reversed supplies.
Most of the registers are only accessible (read and/or
write) during Normal mode or Standby mode. Some other
registers, needed for watchdog initialization and entering
special modes, are only accessible during the Start-up
and/or Restart mode.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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