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參數資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統基礎芯片 |
| 文件頁數： | 34/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
34
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Notes
1.
If the watchdog is triggered with the watchdog OFF code while the UJA1061 is in Standby mode or while the
UJA1061 enters Standby mode, the V1 current monitoring function stays disabled for a period of time equal to the
previous or the default (4096 ms) watchdog period. The default period is selected if the Standby mode is entered
directly with Watchdog OFF mode. After that period, the current monitoring is enabled. Then the behaviour of the
UJA1061 upon a too-high V1 current depends on the setting of the V1CMC bit within the System Configuration
register. If this bit is set (reset option), a too-high V1 current causes an immediate reset. If this bit is not set (Watchdog
Restart option), the watchdog starts a new period without the possibility to be disabled except by being triggered
again with the watchdog OFF code. If the watchdog OFF code is chosen, the watchdog time-out interrupt has no
function.
The Flash Programming mode can be entered only with the consecutive watchdog service sequence ‘Normal
operating mode/Flash Programming mode/Normal operating mode/Flash Programming mode’ using multiple
watchdog period times because access to this register is allowed only while the watchdog is open for write access.
Now the UJA1061 forces a system reset and enters Start-up mode in order to prepare the microcontroller for Flash
memory download. Also the software has to use the Initializing Flash mode within 256 ms in order to enter the Flash
Programming mode of the UJA1061 successfully.
The watchdog is immediately disabled entering Sleep mode with watchdog OFF behaviour selected because
pin RSTN is pulled LOW immediately with the mode change.
Setting of bit SDM is possible only via the Special Mode register and only once after supplying the UJA1061 the first
time with BAT42 voltage. Access of the special mode register has to be executed before the watchdog is initialized,
that is, before the first write to the mode register. Resetting is possible at any time via the mode register. A set SDM
flag disables all reset events caused by the UJA1061 during Normal operating mode (except for wrong mode register
code resets), disables the interrupt time monitoring function during Normal operating mode, the watchdog
initialization time, the reset monitoring and the transitions to Fail-safe mode with the exception of a V1-undervoltage
longerthan256 ms.This bitisset automaticallyifpin TESTisforcedto 7 Vor higherduringpower-on oftheUJA1061
(Software Development mode or forced Normal mode). Watchdog trigger failures resulting only in the interrupt if
enabled in the Interrupt Enable register.
2.
3.
4.
1
EN
Enable
1
0
1
0
EN output pin HIGH
EN output pin LOW
Active mode selected; CAN active; transmissions possible
Auto mode selected; CAN is allowed to fall into low power
0
CM
CAN Mode
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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