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參數(shù)資料
型號(hào)： AD9910BSVZ-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述： SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 10/60頁(yè)
文件大小： 764K
代理商： AD9910BSVZ-REEL
AD9910
Rev. 0 | Page 10 of 60
Table 3. Pin Function Descriptions
Pin No.
1, 20, 72, 86, 87,
93, 97 to 100
2
Mnemonic
NC
I/O
1
Description
Not Connected. Allow device pins to float.
PLL_LOOP_FILTER
I
PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for
details.
Analog Core VDD, 1.8 V Analog Supplies.
Analog DAC VDD, 3.3 V Analog Supplies.
Digital Core VDD, 1.8 V Digital Supplies.
3, 6, 89, 92
74 to 77, 83
17, 23, 30, 47,
57, 64
11, 15, 21, 28, 45,
56, 66
4, 5, 73, 78, 79,
82, 85, 88, 96
13, 16, 22, 29, 46,
51, 58, 65
7
AVDD (1.8V)
AVDD (3.3V)
DVDD (1.8V)
DVDD_I/O (3.3V)
Digital Input/Output VDD, 3.3 V Digital Supplies.
AGND
Analog Ground.
DGND
Digital Ground.
SYNC_IN+
I
Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from
the external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section for details.
Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from
the external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section for details.
Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal
from the internal device subclocks to synchronize external slave devices. See the
Synchronization of Multiple Devices section for details.
Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal
from the internal device subclocks to synchronize external slave devices. See the
Synchronization of Multiple Devices section for details.
Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on
this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN.
Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets
registers to default values.
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section of this
document for further details. If unused, connect to ground.
Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates the
Clock Multiplier PLL has acquired lock to the reference clock input.
RAM Sweep Over, Digital Output (Active High). A high on this pin indicates the RAM sweep
profile has completed.
Parallel Input Bus (Active High).
8
SYNC_IN
I
9
SYNC_OUT+
O
10
SYNC_OUT
O
12
SYNC_SMP_ERR
O
14
MASTER_RESET
I
18
EXT_PWR_DWN
I
19
PLL_LOCK
O
24
RAM_SWP_OVR
O
25 to 27, 31 to 39,
42 to 44, 48
49, 50
40
D<15:0>
I
F<1:0>
PDCLK
I
O
Modulation Format Pin. Digital input to determine the modulation format.
Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a
timing signal for aligning data at the parallel inputs.
Transmit Enable. Digital input (active high). In burst mode communications, a high on this
pin indicates new data for transmission. In continuous mode, this pin remains high.
Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all I/O buffers to the corresponding registers. State changes should be
set up on the SYNC_CLK pin.
Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the
chip, such as I/O_UPDATE and PROFILE<2:0> need to be set up on the rising edge of this
signal.
41
TxENABLE
I
52 to 54
PROFILE<2:0>
I
55
SYNC_CLK
O
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