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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 54/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Bit(s)
12
Rev. 0 | Page 54 of 60
Descriptor
Clear Digital Ramp
Accumulator
Explanation
0 = normal operation of the DRG accumulator (default).
1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset
as long as this bit remains set. This bit is synchronized with either an I/O update or a profile
change and the next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator.
Ineffective unless Bits<9:8> = 11
2
.
0 = normal operation of the OSK amplitude ramp rate timer (default).
1 = OSK amplitude ramp rate timer reloaded anytime I/O_UPDATE is asserted or a profile
change occurs.
The Output Shift Keying Enable bit.
0 = OSK disabled (default).
1 = OSK enabled.
Ineffective unless Bit 9 = 1.
0 = manual OSK enabled (default).
1 = automatic OSK enabled.
This bit is effective without the need for an I/O update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
This bit is effective without the need for an I/O update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
0 = auxiliary DAC clock signals and bias circuits are active (default).
1 = auxiliary DAC clock signals and bias circuits are disabled.
0 = assertion of the EXTPWRDN pin effects full power-down (default).
1 = assertion of the EXTPWRDN pin effects fast recovery power-down.
0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0 = configures the serial I/O port for MSB-first format (default)
1 = configures the serial I/O port for LSB-first format.
11
10
Clear Phase Accumulator
Load ARR @ I/O Update
9
8
7
6
5
4
3
2
1
OSK Enable
Select Auto OSK
Digital Power-Down
DAC Power-Down
REFCLK Input Power-Down
Auxiliary DAC Power-Down
External Power-Down
Control
Not Available
SDIO Input Only
0
LSB First
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