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參數(shù)資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 53/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
REGISTER BIT DESCRIPTIONS
The serial I/O port registers span an address range of 0 to 23
(0x00 to 0x16 in hexadecimal notation). This represents a total
of 24 registers. However, two of these registers are unused
yielding a total of 22 available registers. The unused registers are
Register 5 and Register 6 (0x05 and 0x06, respectively).
Rev. 0 | Page 53 of 60
The number of bytes assigned to the registers varies from
register to register. That is, the registers are not of uniform
depth; each contains the number of bytes necessary for its
particular function. Additionally, the registers are assigned
names according to their functionality. In some cases, a register
is given a mnemonic descriptor. For example, the register at
Serial Address 0x00 is named Control Function Register 1 and
is assigned the mnemonic CFR1.
The following section provides a detailed description of each bit
in the AD9910 register map. Of course, for cases in which a
group of bits serve a specific function, the entire group is
considered as a binary word and described in aggregate.
This section is organized in sequential order of the serial
addresses of the registers. Each subheading includes the register
name and optional register mnemonic (in parentheses). Also
given is the serial address in hexadecimal format and the
number of bytes assigned to the register.
Following each subheading is a table containing the individual
bit descriptions for that particular register. The location of the
bit(s) in the register are indicated by a single number or a pair
of numbers separated by a colon. That is, a pair of numbers
(A:B) indicates a range of bits from the most significant (A) to
the least significant (B). For example, 5:2 implies Bit Position 5
down to Bit Position 2, inclusive, with Bit 0 identifying the LSB
of the register.
Unless otherwise stated, programmed bits are not transferred to
their internal destinations until the assertion of the I/O_UPDATE
pin or a profile change.
Control Function Register 1 (CFR1)
Address 0x00; 4 bytes are assigned to this register.
Table 17. Bit Description for CFR1
Bit(s)
Descriptor
31
RAM Enable
30:29
RAM Playback Destination
28:24
Not Available
23
Control
Explanation
0 = disables RAM functionality (default).
1 = enables RAM functionality (required for both load/retrieve and playback operation).
See Table 12 for details; default is 00
2
.
Ineffective unless Bits<9:8> = 10
2
.
0 = OSK pin inoperative (default).
1 = OSK pin enabled for manual OSK control (see Output Shift Keying (OSK) section for
details).
0 = Inverse sinc filter bypassed (default).
1 = Inverse sinc filter active.
Ineffective unless Bit 31 = 1. These bits are effective without the need for an I/O update.
See Table 14 for details. Default is 0000
2
.
0 = cosine output of the DDS is selected (default).
1 = sine output of the DDS is selected.
Ineffective unless CFR2<19> = 1.
0 = normal operation of the digital ramp timer (default).
1 = digital ramp timer loaded any time I/O_UPDATE is asserted or a profile change occurs.
0 = normal operation of the DRG accumulator (default).
1 = the ramp accumulator is reset for one cycle of the DDS clock after which the
accumulator automatically resumes normal operation. As long as this bit remains set, the
ramp accumulator is momentarily reset each time an I/O update is asserted or a profile
change occurs. This bit is synchronized with either an I/O update or a profile change and
the next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a
profile change occurs.
Manual OSK External
22
21
20:17
Inverse Sinc Filter Enable
Not Available
Internal Profile Control
16
15
14
Select DDS Sine Output
Load LRR @ I/O Update
Autoclear Digital Ramp
Accumulator
13
Autoclear Phase
Accumulator
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