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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 46/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
SERIAL PROGRAMMING
CONTROL INTERFACE—SERIAL I/O
The AD9910 serial port is a flexible, synchronous serial commu-
nications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel 8051 SSR protocols.
Rev. 0 | Page 46 of 60
The interface allows read/write access to all registers that
configure the AD9910. MSB-first or LSB-first transfer formats
are supported. In addition, the serial interface port can be
configured as a single pin input/output (SDIO) allowing a two-
wire interface, or it can be configured as two unidirectional pins
for input/output (SDIO/SDO) enabling a 3-wire interface. Two
optional pins (I/O_RESET and CS) enable greater flexibility for
designing systems with the AD9910.
GENERAL SERIAL I/O OPERATION
There are two phases to a serial communications cycle. The first
is the instruction phase to write the instruction byte into the
AD9910. The instruction byte contains the address of the
register to be accessed (see the Register Map and Bit Descriptions
section) and also defines whether the upcoming data transfer is
a write or read operation.
For a write cycle, Phase 2 represents the data transfer between
the serial port controller to the serial port buffer. The number
of bytes transferred is a function of the register being accessed.
For example, when accessing the Control Function Register 2
(Address 0x01), Phase 2 requires that four bytes be transferred.
Each bit of data is registered on each corresponding rising edge
of SCLK. The serial port controller expects that all bytes of the
register be accessed, otherwise the serial port controller is put
out of sequence for the next communication cycle. However,
one way to write fewer bytes than required is to use the I/O_RESET
pin feature. The I/O_RESET pin function can be used to abort
an I/O operation and reset the pointer of the serial port con-
troller. After an I/O reset, the next byte is the instruction byte.
Note that every completed byte written prior to an I/O reset is
preserved in the serial port buffer. Partial bytes written are not
preserved. At the completion of any communication cycle, the
AD9910 serial port controller expects the next eight rising
SCLK edges to be the instruction byte for the next communi-
cation cycle.
After a write cycle, the programmed data resides in the serial
port buffer and is inactive. I/O_UPDATE transfers data from
the serial port buffer to active registers. The I/O update can
either be sent after each communication cycle or when all serial
operations are complete. In addition, a change in profile pins
can initiate an I/O update.
For a read cycle, Phase 2 is the same as the write cycle with the
following differences: Data is read from the active registers, not
the serial port buffer, and data is driven out on the falling edge
of SCLK.
INSTRUCTION BYTE
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
MSB
D7
D6
D5
R/W
X
X
D4
A4
D3
A3
D2
A2
D1
A1
LSB
D0
A0
R/W—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write. Set
indicates read operation. Cleared indicates a write operation.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t care.
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communications cycle.
SERIAL I/O PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9910 and to run the internal state machines.
CS—Chip Select Bar
Active low input that allows more than one device on the same
serial communications line. The SDO and SDIO pins go to a
high impedance state when this input is high. If driven high
during any communications cycle, that cycle is suspended until
CS is reactivated low. Chip select (CS) can be tied low in
systems that maintain control of SCLK.
SDIO—Serial Data Input/Output
Data is always written into the AD9910 on this pin. However,
this pin can be used as a bidirectional data line. Bit 1 of CFR1
Register Address 0x00 controls the configuration of this pin.
The default is cleared, which configures the SDIO pin as
bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9910 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
I/O_RESET—Input/Output Reset
I/O_RESET synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high
input on the I/O_RESET pin causes the current communication
cycle to abort. After I/O_RESET returns low (Logic 0), another
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