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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 40/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Rev. 0 | Page 40 of 60
0
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
1
2
3
4
5
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
M DDS CLOCK CYCLES
Δ
t
Figure 48. Continuous Recirculate Timing Diagram
RAM Continuous Recirculate Mode
The continuous recirculate mode mimics the ramp up mode,
except that when the state machine reaches the waveform end
address, the next timeout of the internal timer causes the state
machine to jump to the waveform start address. The waveform
repeats until an I/O update or profile change.
The no-dwell high bit is ignored in this mode.
A profile pin state change aborts the current waveform and the
newly selected RAM profile is used to initiate a new waveform.
The RAM_SWP_OVR pin pulses high for two DDS clock cycles
when the state machine reaches the waveform end address.
Continuous recirculate mode is graphically represented in
Figure 48. The circled numbers indicate specific events as
follows:
Event 1—An I/O update or profile change occurs. This event
initializes the state machine to the waveform start address and
sets the RAM_SWP_OVR pin to Logic 0.
Event 2—The state machine reaches the waveform end address
value for the selected profile. The RAM_SWP_OVR pin toggles
to Logic 1 for two DDS clock cycles.
Event 3—The state machine switches to the waveform start
address and continues to increment the address counter.
Event 4—The state machine again reaches the waveform end
address value for the selected profile and the RAM_SWP_OVR
pin toggles to Logic 1 for two DDS clock cycles.
Event 5—The state machine switches to the waveform start
address and continues to increment the address counter.
Event 4 and Event 5—These events repeat until an I/O update
or change in profile.
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