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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 44/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Rev. 0 | Page 44 of 60
LVDS
RECEIVER
PROGAMMABLE
DELAY
5
INTERNAL
CLOCKS
CLOCK
STATE
6
SYNC STATE
PRESET VALUE
SYNC PULSE
SYSCLK
SETUP AND HOLD
VALIDATION
4
D1
D2
Q1
Q2
LOAD
D6
D5
D4
D3
Q6
Q5
Q4
Q3
DELAYED SYNC-IN SIGNAL
SYNC
RECEIVER
DELAY
SYNC
RECEIVER
ENABLE
SYNC_SMP_ERR
SYNC_IN
7
8
12
RISING EDGE
DETECTOR
AND
STROBE
GENERATOR
SYNC
TIMING
VALIDATION
DISABLE
SYNC
VALIDATION
DELAY
0
CLOCK
GENERATOR
Figure 51. Sync Receiver Diagram
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 1
MASTER DEVICE
FPGA
DATA
FPGA
DATA
FPGA
DATA
EDGE
ALIGNED
AT REF_CLK
INPUTS.
EDGE
ALIGNED
AT SYN_IN
INPUTS.
P
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 2
P
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 3
P
(FOR EXAMPLE AD951x)
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
0
CLOCK
SOURCE
Figure 52. Multichip Synchronization Example
The sync receiver accepts a periodic clock signal at the
SYNC_IN pins. This signal is assumed to originate from an
LVDS-compatible driver. The user can delay the SYNC_IN
signal in steps of ~150 ps by programming the 5-bit sync
receiver delay word in the multichip sync register. For the sake
of discussion, the signal at the output of the programmable
delay is referred to as the delayed sync-in signal.
The edge detection logic generates a sync pulse having a dura-
tion of one SYSCLK cycle with a repetition rate equal to the
frequency of the signal applied to the SYNC_IN pins. The sync
pulse is generated as a result of sampling the rising edge of the
delayed sync-in signal with the rising edge of the local SYSCLK.
The sync pulse is routed to the internal clock generator, which
behaves as a presettable counter clocked at the SYSCLK rate.
The sync pulse presets the counter to a predefined state
(programmable via the 6-bit sync state preset value word in the
multichip sync register). The predefined state is only active for a
single SYSCLK cycle, after which the clock generator resumes
cycling through its state sequence at the SYSCLK rate. This
unique state presetting mechanism gives the user the flexibility
to synchronize devices with specific relative clock state offsets
(by assigning a different sync state preset value word to each
device).
Multiple device synchronization is accomplished by providing
each AD9910 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is, they
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