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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 29/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
DRG Slope Control
The heart of the DRG is a 32-bit accumulator clocked by a
programmable timer. The time base for the timer is the DDS
clock, which operates at f
SYSCLK
. The timer establishes
the interval between successive updates of the accumulator.
The positive (+Δt) and negative (Δt) slope step intervals are
independently programmable as given by
P
t
Δ
=
+
Rev. 0 | Page 29 of 60
SYSCLK
f
4
SYSCLK
f
N
t
4
Δ
=
where
P
and
N
are the two 16-bit values stored in the 32-bit digital
ramp rate register and control the step interval. N defines the step
interval of the negative slope portion of the ramp. P defines the step
interval of the positive slope portion of the ramp. The step size of
the positive and negative slope portions of the ramp are controlled
by the 64-bit digital ramp step size register.
The negative step size is programmed as a magnitude value (that is,
an unsigned integer). The relationship between the step size
(positive or negative) values and real units of frequency, phase,
or amplitude depend on the digital ramp destination bits. The
actual frequency, phase, or amplitude step size can be calculated
using the following equations with M representing either N or P
(for Δt and +Δt, respectively):
SYSCLK
f
M
32
2
Step
Frequency
=
=
15
2
M
π
Step
Phase
(radians)
=
13
2
45
M
Step
Phase
(degrees)
FS
I
M
18
2
Step
Amplitude
=
Note that the frequency units are the same as those used to
represent f
SYSCLK
, and the amplitude units are the same as those
used to represent I
FS
(the full-scale output current of the DAC).
The phase and amplitude step size equations yield the average
step size. Due to quantization effects, the actual step size may
vary between the nearest destination LSB above and below the
calculated average.
As described previously, the step interval is controlled by a 16-bit
programmable timer. There are three events that can cause this
timer to be reloaded prior to its expiration. One event is when the
digital ramp enable bit transitions from cleared to set followed by
an I/O update. A second event is a change of state in the DRCTL
pin. The third event is enabled using the Load LRR @ I/O Update
bit (see details in the Register Map and Bit Descriptions section).
DRG Limit Control
The ramp accumulator is followed by limit control logic that
enforces an upper and lower boundary on the output of the ramp
generator. Under no circumstances does the output of the DRG
exceed the programmed limit values while the DRG is enabled. The
limits are set through the 64-bit digital ramp limit register. Note
that the upper limit value must be greater than the lower limit value
to ensure normal operation.
DRG Accumulator Clear
The ramp accumulator can be cleared (that is, reset to 0) under
program control. When the ramp accumulator is cleared, it forces
the DRG output to the lower limit programmed into the digital
ramp limit register.
With the limit control block imbedded in the feedback path of the
accumulator, resetting the accumulator is equivalent to presetting it
to the lower limit value.
Normal Ramp Generation
Normal ramp generation implies that both no-dwell bits are
cleared (see the No-Dwell Ramp Generation section for details).
In Figure 39, a sample ramp waveform is depicted with the
required control signals. The top trace is the DRG output. The
next trace down is the status of the DROVER output pin
(assuming that the DROVER pin active bit is set). The
remaining traces are control bits and control pins. The pertinent
ramp parameters are also identified (upper and lower limits
plus step size and Δt for the positive and negative slopes). Along
the bottom, circled numbers identify specific events. These
events are referred to by number (Event 1 and so on) in the
following paragraphs.
In this particular example, the positive and negative slopes of
the ramp are different to demonstrate the flexibility of the DRG.
The parameters of both slopes can be programmed to make the
positive and negative slopes the same.
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