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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 56/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Bit(s)
6
Rev. 0 | Page 56 of 60
Descriptor
Data Assembler Hold Last
Value
Explanation
Ineffective unless Bit 4 = 1.
0 = the data assembler of the parallel data port internally forces zeros on the data path
and ignores the signals on the D<15:0> and F<1:0> pins while the TxENABLE pin is
Logic 0 (default). This implies that the destination of the data at the parallel data port is
amplitude when TxENABLE is Logic 0.
1 = the data assembler of the parallel data port internally forces the last value received
on the D<15:0> and F<1:0> pins while the TxENABLE pin is Logic 1.
0 = enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization
pulse sampling error.
1 = the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
See the Parallel Data Port Modulation Mode section for more details. Default is 0000
2
.
5
Sync Sample Error Mask
4
3:0
Parallel Data Port Enable
FM Gain
Control Function Register 3 (CFR3)
Address 0x02; 4 bytes are assigned to this register.
Table 19. Bit Descriptions for CFR3
Bit(s)
Descriptor
31:30
DRV0
29:27
Not Available
26:24
VCO SEL
23:22
Not Available
21:19
I
CP
18:16
Not Available
15
Bypass
14
ResetB
13:9
Not Available
8
PLL Enable
7:1
N
Explanation
Controls the REFCLK_OUT pin, (see Table 7 for details); default is 00
2
.
Selects frequency band of the REFCLK PLL VCO, (see Table 8 for details); default is 111
2
.
Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 111
2
.
0 = input divider is selected (default).
1 = input divider is bypassed.
0 = input divider is reset.
1 = input divider operates normally (default).
0 = REFCLK PLL bypassed (default).
1 = REFCLK PLL enabled.
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is
0000000
2
.
REFCLK Input Divider
REFCLK Input Divider
0
Not Available
Auxiliary DAC Control Register
Address 0x03; 4 bytes are assigned to this register.
Table 20. Bit Descriptions for DAC Control Register
Bit(s)
Descriptor
31:8
Not Available
7:0
FSC
Explanation
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary
DAC section); default is 0xFF.
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