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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 2/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
TABLE OF CONTENTS
Features..............................................................................................1
Rev. 0 | Page 2 of 60
Applications.......................................................................................1
Functional Block Diagram..............................................................1
Revision History...............................................................................3
General Description.........................................................................4
Specifications.....................................................................................5
Electrical Specifications...............................................................5
Absolute Maximum Ratings............................................................8
Equivalent Circuits.......................................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Typical Performance Characteristics...........................................12
Application Circuits.......................................................................15
Theory of Operation......................................................................16
Single Tone Mode.......................................................................16
RAM Modulation Mode............................................................17
Digital Ramp Modulation Mode..............................................18
Parallel Data Port Modulation Mode.......................................19
Parallel Data Clock (PDCLK)...............................................19
Transmit Enable (TxENABLE).............................................20
Mode Priority..............................................................................21
Functional Block Detail.................................................................22
DDS Core.....................................................................................22
14-Bit DAC Output....................................................................22
Auxiliary DAC........................................................................23
Inverse Sinc Filter.......................................................................23
Clock Input (REF_CLK)............................................................23
REF_CLK Overview ..............................................................23
Crystal Driven REF_CLK .....................................................24
Direct Driven REF_CLK.......................................................24
Phase-Locked Loop (PLL) Multiplier..................................24
PLL Charge Pump..................................................................25
External PLL Loop Filter Components............................... 25
PLL Lock Indication .................................................................. 26
Output Shift Keying (OSK)....................................................... 26
Manual OSK............................................................................ 26
Automatic OSK....................................................................... 26
Digital Ramp Generator (DRG)............................................... 27
DRG Overview....................................................................... 27
DRG Slope Control................................................................ 29
DRG Limit Control................................................................ 29
DRG Accumulator Clear....................................................... 29
Normal Ramp Generation.................................................... 29
No-Dwell Ramp Generation................................................. 31
DROVER Pin.......................................................................... 31
RAM Control.............................................................................. 32
RAM Overview....................................................................... 32
Load/Retrieve RAM Operation............................................ 32
RAM Playback Operation (Waveform Generation).......... 32
RAM_SWP_OVR (RAM Sweep Over) Pin........................ 33
Overview of RAM Playback Modes .................................... 33
RAM Direct Switch Mode..................................................... 33
RAM Direct Switch Mode with Zero-Crossing................. 34
RAM Ramp Up Mode ........................................................... 34
RAM Ramp Up Internal Profile Control Mode................. 34
Internal Profile Control Continuous Waveform Timing
Diagram................................................................................... 37
RAM Bidirectional Ramp Mode.......................................... 37
RAM Continuous Bidirectional Ramp Mode.................... 38
RAM Continuous Recirculate Mode................................... 40
Additional Features........................................................................ 41
Profiles......................................................................................... 41
I/O_Update Pin.......................................................................... 41
Automatic I/O Update............................................................... 41
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