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參數資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 21/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
MODE PRIORITY
The three different modulation modes generate frequency,
phase, and/or amplitude data destined for the DDS signal
control parameters. In addition, the OSK function generates
amplitude data destined for the DDS. Each of these functions is
independently invoked using the appropriate control bit via the
serial I/O port.
Rev. 0 | Page 21 of 60
The ability to independently activate each of these functions
makes it possible to have multiple data sources attempting to
drive the same DDS signal control parameter. To avoid con-
tention, the AD9910 has a built-in priority system. Table 5
summarizes the priority for each of the DDS signal control
parameters. The rows of the table list data sources for a particular
DDS signal control parameter in descending order of precedence.
For example, if both the RAM and the parallel port are enabled
and both are programmed for frequency as the destination,
then the DDS frequency parameter is driven by the RAM and
not the parallel data port.
Table 5. Data Source Priority
DDS Signal Control Parameters
Phase
Data Source
RAM
Frequency
Conditions
RAM enabled and
data destination is
frequency
DRG enabled and
data destination is
frequency
Parallel data port
enabled and data
destination is
frequency
RAM enabled and
data destination is
phase, amplitude
or polar
DRG enabled and
data destination is
phase or amplitude
Amplitude
Priority
Highest
Priority
Data Source
RAM
Conditions
RAM enabled and
data destination is
phase or polar
DRG enabled and
data destination is
phase
Parallel data port
enabled and data
destination is
phase
Parallel data port
enabled and data
destination is polar
Data Source
OSK generator
Conditions
OSK enabled (auto
mode)
DRG
DRG
ASF register
OSK enabled
(manual mode)
Parallel data
port + FTW
register
Parallel data port
RAM
RAM enabled and
data destination is
amplitude or polar
FTW register
Parallel data port
concatenated with
the POW register
LSBs
POW register
DRG
DRG enabled and
data destination is
amplitude
FTW in active
single tone
profile register
RAM enabled and
destination is
frequency or
amplitude
DRG enabled and
data destination is
frequency or
amplitude
Parallel data port
Parallel data port
enabled and data
destination is
amplitude
Parallel data port
enabled and data
destination is
polar
FTW in active
single tone
profile register
Parallel data port
enabled and data
destination is
phase, amplitude
or polar
None
POW in active
single tone profile
register
Parallel data port
concatenated with
the ASF register
LSBs
FTW in active
single tone
profile register
POW in active
single tone profile
register
Parallel data port
enabled and data
destination is
frequency or
amplitude
None
ASF in active single
tone profile
register
Enable amplitude
scale from Single
Tone Profiles Bit
CFR2<24> set
Lowest
Priority
POW in active
single tone profile
register
No amplitude
scaling
None
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