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參數(shù)資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 47/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
communication cycle can begin, starting with the instruction
byte write.
Rev. 0 | Page 47 of 60
I/O_UPDATE—Input/Output Update
The I/O_UPDATE initiates the transfer of written data from
the I/O port buffer to active registers. I/O_UPDATE is active
on the rising edge and its pulse width must be greater than one
SYNC_CLK period. It is either an input or output pin depending
on the programming of the Internal I/O update active bit.
SERIAL I/O TIMING DIAGRAMS
The diagrams below provide basic examples of the timing
relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
MSB/LSB TRANSFERS
The AD9910 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in Control Function
Register 1 (0x00). The default format is MSB first. If Bit 0 is set
high, the serial port is configured for LSB-first format. If LSB
first is active, all data, including the instruction byte, must
follow LSB-first convention. Note that the highest number
found in the bit range column for each register (see the Register
Map and Bit Descriptions section and Table 16) is the MSB and
the lowest number is the LSB for that register.
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
Figure 54. Serial Port Write Timing, Clock Stall Low
D
O7
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
DON'T CARE
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
SDIO
SCLK
CS
SDO
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
0
Figure 55. 3-Wire Serial Port Read Timing, Clock Stall Low
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
Figure 56. Serial Port Write Timing, Clock Stall High
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
0
Figure 57. 2-Wire Serial Port Read Timing, Clock Stall High
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