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| 型號(hào)： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁(yè)數(shù)： | 16/60頁(yè) |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
THEORY OF OPERATION
The AD9910 has four modes of operation:
Single tone
RAM modulation
Digital ramp modulation
Parallel data port modulation
Rev. 0 | Page 16 of 60
The modes relate to the data source used to supply the DDS
with its signal control parameters: frequency, phase, or ampli-
tude. The partitioning of the data into different combinations
of frequency, phase, and amplitude is handled automatically
based on the mode and/or specific control bits.
In single tone mode, the DDS signal control parameters come
directly from the programming registers associated with the
serial I/O port. In RAM modulation mode, the DDS signal
control parameters are stored in the internal RAM and played
back upon command. In digital ramp modulation mode, the
DDS signal control parameters are delivered by a digital ramp
generator. In parallel data port modulation mode, the DDS
signal control parameters are driven directly into the parallel port.
The various modulation modes generally operate on only one of
the DDS signal control parameters (two in the case of the polar
modulation format). The unmodulated DDS signal control
parameters are stored in their appropriate programming
registers and automatically route to the DDS based on the
selected mode.
A separate output shift keying (OSK) function is also available.
This function employs a separate digital linear ramp generator
that only affects the amplitude parameter of the DDS. The OSK
function has priority over the other data sources that can drive
the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
Although the various modes (including the OSK function) are
described independently, they can be enabled simultaneously.
This provides an unprecedented level of flexibility for generating
complex modulation schemes. However, to avoid multiple data
sources from driving the same DDS signal control parameter,
the device has a built-in priority protocol (see Table 5 in the
Mode Priority section).
SINGLE TONE MODE
In single tone mode, the DDS signal control parameters are
supplied directly from the programming registers. A profile is
an independent register that contains the DDS signal control
parameters. Eight profile registers are available.
Each profile is independently accessible. Use the three external
profile pins (PROFILE<2:0>) to select the desired profile. A
change in the state of the profile pins with the next rising edge
on SYNC_CLK updates the DDS with the parameters specified
by the selected profile.
0
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE
I/O_UPDATE
RAM
POWER
DOWN
CONTROL
E
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (
ω
)
PHASE (
θ
)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
C
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
S
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (
ω
t+
θ
)
Asin (
ω
t+
θ
)
S
S
S
P
P
M
2
2
AUX
DAC
8-BIT
DAC
14-BIT
DDS
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
S
Figure 22. Single Tone Mode
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