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| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 35/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Rev. 0 | Page 35 of 60
Table 14. RAM Internal Profile Control Modes
Internal Profile Control Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Waveform Type
Burst
Burst
Burst
Burst
Burst
Burst
Burst
Continuous
Continuous
Continuous
Continuous
Continuous
Continuous
Continuous
Internal Profile
Control Description
Internal profile control disabled.
Execute Profile 0, then Profile 1, then halt.
Execute Profile 0 to Profile 2, then halt.
Execute Profile 0 to Profile 3, then halt.
Execute Profile 0 to Profile 4, then halt.
Execute Profile 0 to Profile 5, then halt.
Execute Profile 0 to Profile 6, then halt.
Execute Profile 0 to Profile 7, then halt.
Execute Profile 0, then 1, continuously.
Execute Profile 0 to Profile 2, continuously.
Execute Profile 0 to Profile 3, continuously.
Execute Profile 0 to Profile 4, continuously.
Execute Profile 0 to Profile 5, continuously.
Execute Profile 0 to Profile 6, continuously.
Execute Profile 0 to Profile 7, continuously.
Invalid.
If any of the internal profile control bits are set, then the RAM
profile mode control bits of the RAM profile registers are
ignored. The no-dwell high bit is ignored in this mode. The
internal profile control mode is identical to ramp up mode,
except that profile switching is done automatically and
internally; the state of the PROFILE<2:0> pins is ignored.
Profiles cycle according to Table 14.
There are two types of waveform generation types available
under internal profile control; burst waveforms and continuous
waveforms. With both types, the state machine begins with the
waveform specified by the waveform start address, waveform
end address, and address ramp rate in Profile 0. After reaching
the waveform end address of Profile 0, the state machine
automatically advances to the next profile and initiates the
specified waveform as defined by the new profile parameters.
After the state machine reaches the waveform end address of
the new profile it advances to the next profile. This action
continues until the state machine reaches the waveform end
address of the last profile as governed by the internal profile
control bits in Register CFR1 per Table 14.
At this point, the next course of action depends on whether the
waveform type is burst or continuous. For burst waveforms, the
state machine halts operation after reaching the waveform end
address of the final profile. For continuous
waveforms, the state machine automatically jumps to Profile 0
and continues the automatic waveform generation by sequentially
advancing through the profiles. This process continues indefi-
nitely until the internal profile control bits are reprogrammed
and an I/O update is asserted.
A burst waveform timing diagram is exemplified in Figure 44.
The diagram assumes that internal profile control bits in
Control Function Register 1 (CFR1) are programmed as 0010,
the start address in RAM Profile 1 is greater than the end address
in RAM Profile 0, and the start address in RAM Profile 2 is
greater than the end address in RAM Profile 1. However,
understand that the block of RAM associated with each profile
can be chosen arbitrarily based on the waveform start address
and waveform end address for each profile. Furthermore, the
example shows how different Δt values associated with each
profile might be utilized.
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