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| 型號(hào)： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號(hào)處理器與V - Driver和精確定時(shí)⑩發(fā)生器 |
| 文件頁(yè)數(shù)： | 26/88頁(yè) |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
Vertical Pattern (VPAT) Groups
A vertical pattern (VPAT) group defines the individual pulse
pattern for each XV1 to XV13 output signal. Table 14 summarizes
the registers that are available for generating each VPAT group.
The first, second, third, fourth, fifth, and sixth toggle positions
(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5,
XVTOG6) are the pixel locations where the pulse transitions. All
toggle positions are 13-bit values that can be placed anywhere in
the horizontal line.
Rev. 0 | Page 26 of 88
More registers are included in the vertical sequence registers to
specify the output pulses: XV1POL to XV13POL specifies the
start polarity for each signal, VSTART specifies the start
position of the VPAT group, and VLEN designates the total
length of the VPAT group, which determines the number of
pixels between each pattern repetition, if repetitions are used.
To achieve the best possible noise performance, ensure that
VSTART + VLEN < the end of the H-blank region.
Toggle positions programmed to either Pixel 0 or Pixel 8191 are
ignored. The toggle positions of unused XV-channels must be
programmed to either Pixel 0 or Pixel 8191. This prevents unpre-
dictable behavior because the default values of the V-pattern
group registers are unknown.
Table 14. Vertical Pattern Group Registers
Register
Length (Bits)
XVTOG1
13
XVTOG2
13
XVTOG3
13
XVTOG4
13
XVTOG5
13
XVTOG6
13
Range
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
Description
First toggle position within line for each XV1 to XV12 output
Second toggle position
Third toggle position
Fourth toggle position
Fifth toggle position
Sixth toggle position
HD
XV1
PROGRAMMABLE SETTINGS:
1
START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2
FIRST TOGGLE POSITION.
3
SECOND TOGGLE POSITION (A TOTAL OF SIX TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4
TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
4
1
2
3
XV2
1
2
3
XV12
1
2
3
0
Figure 36. Vertical Pattern Group Programmability
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| AD9923ABBCZ | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9923ABBCZRL | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9925BBCZRL | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9923ABBCZ | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9923ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
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