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參數資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發生器 |
| 文件頁數： | 59/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
Table 41. Power-Up Register Write Sequence
Register
Address
SW_RST
0x10
0x20 to 0xFFF
STANDBY
0x00
TEST3
0xEA
OSC_RST
0x16
TGCORE_RSTB
0x15
MASTER
0x20
OUTCONTROL
0x11
SYNCPOL
0x13
Rev. 0 | Page 59 of 88
Data
0x01
User defined
0x04
0x60
0x01
0x01
0x01
0x01
0x01
Description
Resets all registers to default values
Horizontal, vertical, shutter timing
Powers up the AFE
Set TEST3 register to required value
Resets crystal oscillator circuit
Resets internal timing core
Configures master mode
Enables all outputs after SYNC
SYNC active polarity (for software SYNC only)
VD
HD
SUSPEND
SYNC
HL, H1 TO H4, RG,
XV1 TO XV13,
VSG1 TO VSG8, SUBCK
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure 76. SYNC Timing to Synchronize AD9923A with External Timing
0
Generating Software Sync Without External Sync Signal
If an external sync pulse is not available, it is possible to generate
an internal sync pulse by writing to the SYNCPOL register
(Address 0x13). If the software SYNC option is used, the SYNC
input (Pin 35) should be low (VSS) during the power-up proce-
dure. After the power-up procedure is complete, the SYNC pin
can be used as an output by setting the SYNCENABLE register
low (Address 0x12).
After power-up, follow Step 1 to Step 9 of the procedure in the
Recommended Power-Up Sequence for Master Mode section.
For Step 10, instead of using the external sync pulse, write 1 to
the SYNCPOL register to generate an internal sync pulse and
begin the timing operation.
SYNC During Master Mode Operation
The SYNC input can be used anytime during master mode
operation to synchronize the AD9923A counters with external
timing, as shown in Figure 76.
To suspend operation of the digital outputs during the SYNC
operation, set the SYNCSUSPEND register (Address 0x14) to 1. If
SYNCSUSPEND = 1, the polarities of the outputs are held at the
same state as when OUTCONTROL = low, as shown in Table 42
and Table 43.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure described for master mode operation, with
two exceptions:
Eliminate Step 8. Do not configure the part for master
mode timing.
No sync pulse is required in slave mode. Substitute Step 10
with starting the external VD and HD signals. This
synchronizes the part, allows the register updates, and
starts the timing operation.
Note that DCLK does not begin to transition until Step 7 is
complete.
When the AD9923A is in slave mode, the VD/HD inputs
synchronize the internal counters. After a falling edge of VD,
there is a latency of 34 master clock edges (CLI) after the falling
edge of HD until the internal H-counter is reset. The reset
operation is shown in Figure 77.
Note that if SHDLOC is set so that the 3 ns minimum delay
between the rising edge of SLI and the falling edge of the
internal SHD signal is not met, the internal H-counter can reset
after only 33 master clock edges (CLI).
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