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參數資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發生器 |
| 文件頁數： | 38/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
MODE Register
The MODE register is a single register that selects the field timing
of the AD9923A. Typically, all field, V-sequence, and V-pattern
group information is programmed into the AD9923A at startup.
During operation, the MODE register allows the user to select
any combination of field timing to meet the current requirements
of the system. Using the MODE register in conjunction with
preprogrammed timing greatly reduces the system programming
requirements during camera operation. Only a few register writes
are required when the camera operating mode is changed rather
than having to rewrite the vertical timing information with each
camera mode change.
Rev. 0 | Page 38 of 88
A basic still camera application can require five fields of vertical
timing—one for draft mode operation, one for autofocusing, and
three for still image readout. The register timing information for
the five fields is loaded at startup. Depending on how the camera
is being used, the MODE register selects which field timing is
active during camera operation.
Table 20 shows how the MODE register bits are used. Unlike
other registers, the MODE register uses 10 address bits as data
bits to increase the total register size to 38 bits. The address
MSBs, A11 and A10, are 1 and 0, respectively, and are used to
specify the MODE register write. The three MSBs, D37, D36,
and D35 are used to specify the number of fields used. A value
from 1 to 7 can be selected using these three bits. The remaining
register bits are divided into five-bit sections to select which
programmed fields are used and in which order. Up to seven
fields can be used in a single MODE write. The AD9923A starts
with the field timing specified by the first field bit, and switches
to the timing specified by the second field bit on the next VD,
and so on.
After completing the number of fields specified in Bit D37 to
Bit D35, the timing generator of the AD9923A repeats itself by
starting at the first field. This continues until a new write to the
MODE register occurs. Figure 51 shows MODE register settings
for various field configurations.
Table 20. Mode Register Contents—VD Updated
Address (Binary)
12b10_xx_xxxx_xxxx
Data Bits
[37:0]
[37:35]
[34:30]
[29:25]
[24:20]
[19:15]
[14:10]
[9:5]
[4:0]
Default Value
0
Description
A11, A10 must be set to 0x10; remaining A9:A0 bits used for D37:D28
Number of fields (maximum of seven)
Selected field for Field 7
Selected field for Field 5
Selected field for Field 6
Selected field for Field 4
Selected field for Field 3
Selected field for Field 2
Selected field for Field 1
EXAMPLE 1:
TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x9800000820
EXAMPLE 2:
TOTAL FIELDS = 1, FIRST FIELD = FIELD 3
MODE REGISTER CONTENTS = 0x8800000003
EXAMPLE 3:
TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2
MODE REGISTER CONTENTS = 0xA000011025
FIELD 3
FIELD 0
FIELD 1
FIELD 2
FIELD 5
FIELD 1
FIELD 4
FIELD 2
0
Figure 51. Using the Mode Register to Select Field Timing
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