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參數資料
型號: AD9923A
廠商: Analog Devices, Inc.
英文描述: CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述: CCD信號處理器與V - Driver和精確定時⑩發生器
文件頁數: 48/88頁
文件大小: 852K
代理商: AD9923A
AD9923A
SUBCK: Suppression
Normally, the SUBCK begins pulsing on the line following the
sensor gate line (VSG). Some CCDs require suppressing the
SUBCK pulse for one or more lines following the VSG line. The
SUBCKSUPPRESS register enables such suppression.
Rev. 0 | Page 48 of 88
Readout After Exposure
After the exposure, the readout of the CCD data occurs, beginning
with the sensor gate (VSG) operation. By default, the AD9923A
generates VSG pulses in every field. When only a single exposure
and readout frame are needed, as is the case in the CCD preview
mode, the VSG and SUBCK pulses can operate in every field.
However, often during readout, the SUBCK output must be
suppressed until the readout is complete. The READOUTNUM
register specifies the number of additional fields after the exposure
to continue the suppression of SUBCK. READOUTNUM can be
programmed for 0 to 7 fields, and should be preprogrammed at
startup, not at the same time as the exposure write. A typical
interlaced CCD frame readout mode generally requires two fields
of SUBCK suppression (READOUTNUM = 2) during readout.
A three-field, six-phase CCD requires three fields of SUBCK
suppression after the readout begins (READOUTNUM = 3).
If SUBCK output is required to initiate backup during the last field
of readout, program the READOUTNUM register to one less
than the total number of CCD readout fields. Similar to the
exposure operation, the readout operation must be triggered
using the TRIGGER register.
SUBCK: Additional Masking
The SUBCKMASK register (Address 0x65) allows more complex
SUBCK masking. If SUBCKMASK = 1, it starts masking the
SUBCK at the next VD edge. If SUBCKMASK = 2, it enables
users to select the internal SHUT3 signal and create a custom
SUBCK masking pattern that spans several fields.
When generating an exposure by using the TRIGGER register,
as previously described in the Readout After Exposure section,
the AD9923A outputs the SUBCK and VSG signals on every
field by default. This works well for continuous, single field
exposure and readout operations, such as those in the CCD live
preview mode. However, if the CCD requires a longer exposure
time, or if multiple readout fields are needed, the TRIGGER
register is needed to initiate specific exposure and readout
sequences.
Typically, the exposure and readout bits in the TRIGGER register
are used together. This initiates a complete exposure-plus-readout
operation. After the exposure, the readout occurs automatically.
The values in the EXPOSURE and READOUTNUM registers
determine the length of each operation.
It is possible to independently trigger the readout operation
without triggering the exposure operation. This causes the readout
to occur at the next VD, and the SUBCK output is suppressed
according to the value set in the READOUTNUM register.
The TRIGGER register also controls the SHUT and VSUB signals.
Each signal is individually controlled, but dependent on the
triggering of the exposure and readout operations. See Figure 71
for a complete example of triggering the exposure and readout
operations.
Alternatively, it is possible to manually control the exposure and
readout operations by carefully updating the SUBCKSUPPRESS
and VSG masking registers upon every VD field. As described in
the following sections, it is possible to have partial or full manual
control of the shutter signals. This allows greater flexibility in
generating custom exposure/readout/shutter signal timing.
相關PDF資料
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AD9923ABBCZ CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
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AD9923ABBCZRL 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG,串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:20-TSSOP 包裝:管件
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