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參數資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發生器 |
| 文件頁數： | 37/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light sensitive image area
into the light shielded vertical registers. From the light shielded
vertical registers, the image is then read line-by-line using the
XV1 to XV13 vertical transfer pulses in conjunction with the
high speed horizontal clocks.
Rev. 0 | Page 37 of 88
Table 19 summarizes the VSG pattern registers. The AD9923A
has eight VSG outputs, VSG1 to VSG8. Each output can be
assigned to one of eight programmed patterns by using the
SGPATSEL register. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start
polarity (SGPOL), first toggle position (SGTOG1), and second
toggle position (SGTOG2). The active line where the VSG1 to
VSG8 pulses occur is programmable using the SGACTLINE1
and SGACTLINE2 registers. Additionally, any of the VSG1 to
VSG8 pulses can be individually disabled using the SGMASK
register. The individual masking allows all SG patterns to be
preprogrammed, and the appropriate pulses for each field can
be separately enabled. For maximum flexibility, the SGPATSEL,
SGMASK, and SGACTLINE registers are separately programmable
for each field. More detail is given in the Complete Field:
Combining V-Sequences section.
Additionally, there is the SGMASK_BYP register (Address 0x59)
that overrides SG masking in the field registers. The SGMASK_BYP
register allows sensor gate masking to be changed without
modifying the field register values. The SGMASK_BYP register
is SCK updated; therefore, the new SG-masking values update
immediately.
Table 19. VSG Pattern Registers
1
Register
SGPOL
SGTOG1
Length
(Bits)
1
13
Range
High/low
0 to 8191 pixel
location
0 to 8191 pixel
location
High/low for
each VSG
0 or 1
Description
Sensor gate starting polarity for SG patterns 0 to 7.
First toggle position for SG patterns 0 to 7.
SGTOG2
13
Second toggle position for SG patterns 0 to 7.
SGMASK_BYP
8
SGMASK Bypass. This register overrides the SGMASK values in each field register. One bit
for each output, where Bit[0] is for VSG1 output and Bit 7 is for VSG8 output.
0 = active.
1 = mask output.
1: enables SGMASK bypass.
SGMASK_BYP_EN
1
See field registers in Table 16.
1
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1
START POLARITY OF PULSE.
2
FIRST TOGGLE POSITION.
3
SECOND TOGGLE POSITION.
4
ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).
Figure 50. Vertical Sensor Gate Pulse Placement
VSG PATTERNS
4
1
2
3
0
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