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參數資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發生器 |
| 文件頁數： | 58/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
Recommended Power-Up Sequence for Master Mode
When the AD9923A is powered up, the following sequence is
recommended (see Figure 75):
Rev. 0 | Page 58 of 88
1.
Turn on the +3 V power supplies for the AD9923A, and
start the master clock (CLI).
2.
Turn on the V-driver supplies (VH and VL). There are no
restrictions on the order in which VH and VL are turned on.
3.
Reset the internal AD9923A registers by writing 1 to the
SW_RST register (Address 0x10).
4.
Load the required registers to configure the required
VPAT group, V-sequence, field timing information, high
speed timing, horizontal timing, and shutter timing
information.
5.
To place the part into normal power operation, write 0x04
to the AFE STANDBY register (Bits[1:0], Address 0x00)
and 0x60 to TEST3 Register 0xEA. If the CLO output is
being used to drive a crystal, also power up the CLO
oscillator by writing 1 to Register 0x16.
6.
By default, the internal timing core is held in a reset state
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x15) to start the
internal timing core operation. If a 2× clock is used for the
CLI input, set the CLIDIVIDE register (Address 0x30) to
1 before resetting the timing core. It is important to wait
at least 500 μs after starting the master clock (CLI) before
resetting the timing core, especially if using a crystal or
crystal oscillator.
7.
Configure the AD9923A for master mode timing by
writing 1 to the MASTER register (Address 0x20).
8.
Bring the VDR_EN signal high to +3 V to enable the
V-driver outputs. If VDR_EN = 0 V, all V-driver outputs =
VM, and SUBCK = VLL.
9.
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge.
10.
Generate a SYNC event. If SYNC is high at power-up,
bring SYNC input low for a minimum of 100 ns. Then,
bring SYNC high. This causes the internal counters to
reset and starts a VD/HD operation. The first VD/HD
edge allows VD register updates to occur, including
OUTCONTROL to enable all outputs. If an external
SYNC pulse is not available, generate an internal SYNC
pulse by writing to the SYNCPOL register as described in
the Generating Software Sync Without External Sync
Signal section.
POWER
SUPPLIES
SERIAL
WRITES
VD
(OUTPUT)
1H
FIRST FIELD
SYNC
(INPUT)
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE.
H1/H3, RG, DCLK, STROBE, MSHUT, VSUB
(AND INTERNAL XV1 TO XV13, VSG1 TO VSG8, XSBUCK, XSUBCNT)
CLI
(INPUT)
HD
(OUTPUT)
t
SYNC
0V
VH SUPPLY
VL SUPPLY
(HI-Z BY DEFAULT)
(HI-Z BY DEFAULT)
2
3
4
5
6
7
9
10
1V
5
1
+3V SUPPLIES
VDR_EN
8
0V
+3V
VH
VM
VL
V1 TO V13
VM
0
Figure 75. Recommended Power-Up Sequence and Synchronization, Master Mode
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